SAMA5D4-EK: NSH should run at 528MHz

arch/arm/src/sama5/chip/sam_pmc.h

@@ -420,7 +420,7 @@
 #define PMC_PCR_CMD                    (1 << 12) /* Bit 12: Command */
 
 #ifdef ATSAMA5D3
-#  define SAMA5_HAVE_PMC_PCR           1         /* Supports conditional compilation */
+#  define SAMA5_HAVE_PMC_PCR_DIV       1         /* Supports conditional compilation */
 #  define PMC_PCR_DIV_SHIFT            (16)      /* Bits 16-17: Divisor Value */
 #  define PMC_PCR_DIV_MASK             (3 << PMC_PCR_DIV_SHIFT)
 #    define PMC_PCR_DIV1               (0 << PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK */

arch/arm/src/sama5/sam_twi.c

@@ -1169,6 +1169,8 @@ static void twi_hw_initialize(struct twi_dev_s *priv, unsigned int pid,
   mck = BOARD_MCK_FREQUENCY;
 
 #ifdef SAMA5_HAVE_PMC_PCR_DIV
+  /* Select the optimal value for the PCR DIV field */
+
   DEBUGASSERT((mck >> 3) <= TWI_MAX_FREQUENCY);
   if (mck <= TWI_MAX_FREQUENCY)
     {
@@ -1193,7 +1195,7 @@ static void twi_hw_initialize(struct twi_dev_s *priv, unsigned int pid,
 
 #else
   /* No DIV field in the PCR register */
- 
+
   priv->frequency     = mck;
   regval              = 0;
 

configs/sama5d4-ek/README.txt

@@ -1760,11 +1760,6 @@ USB High-Speed Host
     Application Configuration -> NSH Library
       CONFIG_NSH_ARCHINIT=y                 : NSH board-initialization
 
-  NOTE:  When OHCI is selected, the SAMA5 will operate at 384MHz instead of
-  396MHz.  This is so that the PLL generates a frequency which is a multiple
-  of the 48MHz needed for OHCI.  The delay loop calibration values that are
-  used will be off slightly because of this.
-
   EHCI
   ----
 
@@ -3023,29 +3018,12 @@ Configurations
      create a very corrupt configuration that may not be easy to recover
      from.
 
-  4. The SAMA5Dx is running at 396MHz by default in these configurations.
-     This is because the original timing for the PLLs, NOR FLASH, and SDRAM
-     came from the Atmel NoOS sample code which runs at that rate.
-
-     The SAMA5Dx is capable of running at 528MHz, however, and is easily
-     re-configured:
+  4. The SAMA5Dx is running at 528MHz by default in these configurations.
 
        Board Selection -> CPU Frequency
-         CONFIG_SAMA5D4EK_396MHZ=n     # Disable 396MHz operation
-         CONFIG_SAMA5D4EK_528MHZ=y     # Enable 528MHz operation
-
-     If you switch to 528MHz, you should also check the loop calibration
-     value in your .config file.  Of course, it would be best to re-calibrate
-     the timing loop, but these values should get you in the ballpark:
-
-       CONFIG_BOARD_LOOPSPERMSEC=49341  # Calibrated on SAMA5D3-EK at 396MHz
-                                        # running from ISRAM
-       CONFIG_BOARD_LOOPSPERMSEC=65775  # Calibrated on SAMA5D3-Xplained at
-                                        # 528MHz running from SDRAM
-
-     Operation at 528MHz has been verified but is not the default in these
-     configurations because most testing was done at 396MHz.  NAND has not
-     been verified at these rates.
+         CONFIG_SAMA5D4EK_528MHZ=y       : Enable 528MHz operation
+         CONFIG_BOARD_LOOPSPERMSEC=65775 : Calibrated on SAMA5D3-Xplained at
+                                         : 528MHz running from SDRAM
 
   Configuration Sub-directories
   -----------------------------

configs/sama5d4-ek/nsh/defconfig

@@ -351,8 +351,8 @@ CONFIG_NSH_MMCSDSLOTNO=0
 # Board-Specific Options
 #
 # CONFIG_SAMA5D4EK_384MHZ is not set
-CONFIG_SAMA5D4EK_396MHZ=y
-# CONFIG_SAMA5D4EK_528MHZ is not set
+# CONFIG_SAMA5D4EK_396MHZ is not set
+CONFIG_SAMA5D4EK_528MHZ=y
 CONFIG_SAMA5D4EK_DRAM_BOOT=y
 
 #