From a722b74de704c9929b91ed4ab1124fa2b5ed6afd Mon Sep 17 00:00:00 2001 From: YAMAMOTO Takashi Date: Fri, 30 Aug 2024 00:22:24 +0900 Subject: [PATCH] esp32: cache_sram_mmu_set: update the correct register bits --- arch/xtensa/src/esp32/esp32_spiram.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_spiram.c b/arch/xtensa/src/esp32/esp32_spiram.c index 7b62a51acd..942b414c11 100644 --- a/arch/xtensa/src/esp32/esp32_spiram.c +++ b/arch/xtensa/src/esp32/esp32_spiram.c @@ -199,15 +199,15 @@ unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, if (cpu_no == 0) { regval = getreg32(DPORT_PRO_CACHE_CTRL1_REG); - regval &= ~DPORT_PRO_CMMU_SRAM_PAGE_MODE; - regval |= mask_s; + regval &= ~DPORT_PRO_CMMU_SRAM_PAGE_MODE_M; + regval |= mask_s << DPORT_PRO_CMMU_SRAM_PAGE_MODE_S; putreg32(regval, DPORT_PRO_CACHE_CTRL1_REG); } else { regval = getreg32(DPORT_APP_CACHE_CTRL1_REG); - regval &= ~DPORT_APP_CMMU_SRAM_PAGE_MODE; - regval |= mask_s; + regval &= ~DPORT_APP_CMMU_SRAM_PAGE_MODE_M; + regval |= mask_s << DPORT_APP_CMMU_SRAM_PAGE_MODE_S; putreg32(regval, DPORT_APP_CACHE_CTRL1_REG); }