PIC32MZ: Fix some PLL setup logic
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a42813c756
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@ -207,21 +207,21 @@
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/* System PLL Divided Input Clock Frequency Range bits */
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#if BOARD_PLL_INPUT < 5000000
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# error BOARD_PLL_INPUT too low
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#if (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 5000000
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# error BOARD_PLL_INPUT / BOARD_PLL_IDIV too low
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# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_BYPASS /* < 5 MHz */
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#elif BOARD_PLL_INPUT < 9000000
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#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 9000000
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# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_5_10MHZ /* 5-10 MHz */
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#elif BOARD_PLL_INPUT < 14500000
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#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 14500000
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# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_8_16MHZ /* 8-16 MHz */
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#elif BOARD_PLL_INPUT < 23500000
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#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 23500000
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# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_13_26MHZ /* 13-26 MHz */
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#elif BOARD_PLL_INPUT < 39000000
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#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 39000000
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# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_21_42MHZ /* 21-42 MHz */
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#elif BOARD_PLL_INPUT < 64000000
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#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 64000000
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# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_34_64MHZ /* 36-64 MHz */
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#else
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# error BOARD_PLL_INPUT too high
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# error BOARD_PLL_INPUT / BOARD_PLL_IDIV too high
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# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_34_64MHZ /* 36-64 MHz */
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#endif
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@ -59,7 +59,7 @@
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/* Oscillator modes */
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#define BOARD_FNOSC_POSC 1 /* Use primary oscillator */
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#define BOARD_FNOSC_SPLL 1 /* Use system PLL */
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#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */
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/* PLL configuration and resulting CPU clock.
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