diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h b/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
index a040d5cc96..6ec21964f9 100644
--- a/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
+++ b/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
@@ -570,15 +570,15 @@
 
 /* PLLSAI configuration register */
 
-#define RCC_PLLSAICFG_PLLSAIN_SHIFT  (6)      /* Bits 6-14: PLLSAI divider (N) for VCO */
-#define RCC_PLLSAICFG_PLLSAIN_MASK   (0x1ff << RCC_PLLSAICFG_PLLSAIN_SHIFT)
-#  define RCC_PLLSAICFG_PLLSAIN(n)   ((n) << RCC_PLLSAICFG_PLLSAIN_SHIFT)
+#define RCC_PLLSAICFGR_PLLSAIN_SHIFT (6)      /* Bits 6-14: PLLSAI divider (N) for VCO */
+#define RCC_PLLSAICFGR_PLLSAIN_MASK  (0x1ff << RCC_PLLSAICFGR_PLLSAIN_SHIFT)
+#  define RCC_PLLSAICFGR_PLLSAIN(n)  ((n) << RCC_PLLSAICFGR_PLLSAIN_SHIFT)
 #define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24)     /* Bits 24-27: PLLSAI division factor for SAI clock */
 #define RCC_PLLSAICFGR_PLLSAIQ_MASK  (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
-#  define RCC_PLLSAICFG_PLLSAIQ(n)   ((n) << RCC_PLLSAICFG_PLLSAIQ_SHIFT)
+#  define RCC_PLLSAICFGR_PLLSAIQ(n)  ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
 #define RCC_PLLSAICFGR_PLLSAIR_SHIFT (28)     /* Bits 28-30: PLLSAI division factor for LCD clock */
 #define RCC_PLLSAICFGR_PLLSAIR_MASK  (7 << RCC_PLLSAICFGR_PLLSAIR_SHIFT)
-#  define RCC_PLLSAICFG_PLLSAIR(n)   ((n) << RCC_PLLSAICFG_PLLSAIR_SHIFT)
+#  define RCC_PLLSAICFGR_PLLSAIR(n)  ((n) << RCC_PLLSAICFGR_PLLSAIR_SHIFT)
 
 /* Dedicated clocks configuration register */