STM32 F7: Fix a few of the many Ethernet compilation issues (still more)
This commit is contained in:
Gregory Nutt
parent
1d3329e6d9
commit
9c9c31eca8
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@ -123,71 +123,71 @@
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/* Register Base Addresses **************************************************************************/
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/* MAC Registers */
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#define STM32_ETH_MACCR (STM32_ETHERNET_BASE+STM32_ETH_MACCR_OFFSET)
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#define STM32_ETH_MACFFR (STM32_ETHERNET_BASE+STM32_ETH_MACFFR_OFFSET)
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#define STM32_ETH_MACHTHR (STM32_ETHERNET_BASE+STM32_ETH_MACHTHR_OFFSET)
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#define STM32_ETH_MACHTLR (STM32_ETHERNET_BASE+STM32_ETH_MACHTLR_OFFSET)
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#define STM32_ETH_MACMIIAR (STM32_ETHERNET_BASE+STM32_ETH_MACMIIAR_OFFSET)
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#define STM32_ETH_MACMIIDR (STM32_ETHERNET_BASE+STM32_ETH_MACMIIDR_OFFSET)
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#define STM32_ETH_MACFCR (STM32_ETHERNET_BASE+STM32_ETH_MACFCR_OFFSET)
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#define STM32_ETH_MACVLANTR (STM32_ETHERNET_BASE+STM32_ETH_MACVLANTR_OFFSET)
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#define STM32_ETH_MACRWUFFR (STM32_ETHERNET_BASE+STM32_ETH_MACRWUFFR_OFFSET)
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#define STM32_ETH_MACPMTCSR (STM32_ETHERNET_BASE+STM32_ETH_MACPMTCSR_OFFSET)
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#define STM32_ETH_MACDBGR (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET)
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#define STM32_ETH_MACSR (STM32_ETHERNET_BASE+STM32_ETH_MACSR_OFFSET)
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#define STM32_ETH_MACIMR (STM32_ETHERNET_BASE+STM32_ETH_MACIMR_OFFSET)
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#define STM32_ETH_MACA0HR (STM32_ETHERNET_BASE+STM32_ETH_MACA0HR_OFFSET)
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#define STM32_ETH_MACA0LR (STM32_ETHERNET_BASE+STM32_ETH_MACA0LR_OFFSET)
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#define STM32_ETH_MACA1HR (STM32_ETHERNET_BASE+STM32_ETH_MACA1HR_OFFSET)
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#define STM32_ETH_MACA1LR (STM32_ETHERNET_BASE+STM32_ETH_MACA1LR_OFFSET)
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#define STM32_ETH_MACA2HR (STM32_ETHERNET_BASE+STM32_ETH_MACA2HR_OFFSET)
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#define STM32_ETH_MACA2LR (STM32_ETHERNET_BASE+STM32_ETH_MACA2LR_OFFSET)
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#define STM32_ETH_MACA3HR (STM32_ETHERNET_BASE+STM32_ETH_MACA3HR_OFFSET)
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#define STM32_ETH_MACA3LR (STM32_ETHERNET_BASE+STM32_ETH_MACA3LR_OFFSET)
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#define STM32_ETH_MACCR (STM32_ETHMAC_BASE+STM32_ETH_MACCR_OFFSET)
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#define STM32_ETH_MACFFR (STM32_ETHMAC_BASE+STM32_ETH_MACFFR_OFFSET)
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#define STM32_ETH_MACHTHR (STM32_ETHMAC_BASE+STM32_ETH_MACHTHR_OFFSET)
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#define STM32_ETH_MACHTLR (STM32_ETHMAC_BASE+STM32_ETH_MACHTLR_OFFSET)
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#define STM32_ETH_MACMIIAR (STM32_ETHMAC_BASE+STM32_ETH_MACMIIAR_OFFSET)
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#define STM32_ETH_MACMIIDR (STM32_ETHMAC_BASE+STM32_ETH_MACMIIDR_OFFSET)
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#define STM32_ETH_MACFCR (STM32_ETHMAC_BASE+STM32_ETH_MACFCR_OFFSET)
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#define STM32_ETH_MACVLANTR (STM32_ETHMAC_BASE+STM32_ETH_MACVLANTR_OFFSET)
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#define STM32_ETH_MACRWUFFR (STM32_ETHMAC_BASE+STM32_ETH_MACRWUFFR_OFFSET)
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#define STM32_ETH_MACPMTCSR (STM32_ETHMAC_BASE+STM32_ETH_MACPMTCSR_OFFSET)
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#define STM32_ETH_MACDBGR (STM32_ETHMAC_BASE+STM32_ETH_MACDBGR_OFFSET)
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#define STM32_ETH_MACSR (STM32_ETHMAC_BASE+STM32_ETH_MACSR_OFFSET)
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#define STM32_ETH_MACIMR (STM32_ETHMAC_BASE+STM32_ETH_MACIMR_OFFSET)
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#define STM32_ETH_MACA0HR (STM32_ETHMAC_BASE+STM32_ETH_MACA0HR_OFFSET)
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#define STM32_ETH_MACA0LR (STM32_ETHMAC_BASE+STM32_ETH_MACA0LR_OFFSET)
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#define STM32_ETH_MACA1HR (STM32_ETHMAC_BASE+STM32_ETH_MACA1HR_OFFSET)
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#define STM32_ETH_MACA1LR (STM32_ETHMAC_BASE+STM32_ETH_MACA1LR_OFFSET)
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#define STM32_ETH_MACA2HR (STM32_ETHMAC_BASE+STM32_ETH_MACA2HR_OFFSET)
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#define STM32_ETH_MACA2LR (STM32_ETHMAC_BASE+STM32_ETH_MACA2LR_OFFSET)
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#define STM32_ETH_MACA3HR (STM32_ETHMAC_BASE+STM32_ETH_MACA3HR_OFFSET)
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#define STM32_ETH_MACA3LR (STM32_ETHMAC_BASE+STM32_ETH_MACA3LR_OFFSET)
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/* MMC Registers */
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#define STM32_ETH_MMCC (STM32_ETHERNET_BASE+STM32_ETH_MMCCR_OFFSET)
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#define STM32_ETH_MMCRIR (STM32_ETHERNET_BASE+STM32_ETH_MMCRIR_OFFSET)
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#define STM32_ETH_MMCTIR (STM32_ETHERNET_BASE+STM32_ETH_MMCTIR_OFFSET)
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#define STM32_ETH_MMCRIMR (STM32_ETHERNET_BASE+STM32_ETH_MMCRIMR_OFFSET)
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#define STM32_ETH_MMCTIMR (STM32_ETHERNET_BASE+STM32_ETH_MMCTIMR_OFFSET)
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#define STM32_ETH_MMCTGFSCCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFSCCR_OFFSET)
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#define STM32_ETH_MMCTGFMSCCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFMSCCR_OFFSET)
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#define STM32_ETH_MMCTGFCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFCR_OFFSET)
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#define STM32_ETH_MMCRFCECR (STM32_ETHERNET_BASE+STM32_ETH_MMCRFCECR_OFFSET)
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#define STM32_ETH_MMCRFAECR (STM32_ETHERNET_BASE+STM32_ETH_MMCRFAECR_OFFSET)
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#define STM32_ETH_MMCRGUFCR (STM32_ETHERNET_BASE+STM32_ETH_MMCRGUFCR_OFFSET)
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#define STM32_ETH_MMCC (STM32_ETHMAC_BASE+STM32_ETH_MMCCR_OFFSET)
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#define STM32_ETH_MMCRIR (STM32_ETHMAC_BASE+STM32_ETH_MMCRIR_OFFSET)
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#define STM32_ETH_MMCTIR (STM32_ETHMAC_BASE+STM32_ETH_MMCTIR_OFFSET)
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#define STM32_ETH_MMCRIMR (STM32_ETHMAC_BASE+STM32_ETH_MMCRIMR_OFFSET)
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#define STM32_ETH_MMCTIMR (STM32_ETHMAC_BASE+STM32_ETH_MMCTIMR_OFFSET)
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#define STM32_ETH_MMCTGFSCCR (STM32_ETHMAC_BASE+STM32_ETH_MMCTGFSCCR_OFFSET)
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#define STM32_ETH_MMCTGFMSCCR (STM32_ETHMAC_BASE+STM32_ETH_MMCTGFMSCCR_OFFSET)
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#define STM32_ETH_MMCTGFCR (STM32_ETHMAC_BASE+STM32_ETH_MMCTGFCR_OFFSET)
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#define STM32_ETH_MMCRFCECR (STM32_ETHMAC_BASE+STM32_ETH_MMCRFCECR_OFFSET)
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#define STM32_ETH_MMCRFAECR (STM32_ETHMAC_BASE+STM32_ETH_MMCRFAECR_OFFSET)
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#define STM32_ETH_MMCRGUFCR (STM32_ETHMAC_BASE+STM32_ETH_MMCRGUFCR_OFFSET)
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/* IEEE 1588 time stamp registers */
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#define STM32_ETH_PTPTSCR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSCR_OFFSET)
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#define STM32_ETH_PTPSSIR (STM32_ETHERNET_BASE+STM32_ETH_PTPSSIR_OFFSET)
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#define STM32_ETH_PTPTSHR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSHR_OFFSET)
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#define STM32_ETH_PTPTSLR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSLR_OFFSET)
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#define STM32_ETH_PTPTSHUR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSHUR_OFFSET)
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#define STM32_ETH_PTPTSLUR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSLUR_OFFSET)
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#define STM32_ETH_PTPTSAR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSAR_OFFSET)
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#define STM32_ETH_PTPTTHR (STM32_ETHERNET_BASE+STM32_ETH_PTPTTHR_OFFSET)
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#define STM32_ETH_PTPTTLR (STM32_ETHERNET_BASE+STM32_ETH_PTPTTLR_OFFSET)
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#define STM32_ETH_PTPTSSR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSSR_OFFSET)
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#define STM32_ETH_PTPTSCR (STM32_ETHMAC_BASE+STM32_ETH_PTPTSCR_OFFSET)
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#define STM32_ETH_PTPSSIR (STM32_ETHMAC_BASE+STM32_ETH_PTPSSIR_OFFSET)
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#define STM32_ETH_PTPTSHR (STM32_ETHMAC_BASE+STM32_ETH_PTPTSHR_OFFSET)
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#define STM32_ETH_PTPTSLR (STM32_ETHMAC_BASE+STM32_ETH_PTPTSLR_OFFSET)
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#define STM32_ETH_PTPTSHUR (STM32_ETHMAC_BASE+STM32_ETH_PTPTSHUR_OFFSET)
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#define STM32_ETH_PTPTSLUR (STM32_ETHMAC_BASE+STM32_ETH_PTPTSLUR_OFFSET)
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#define STM32_ETH_PTPTSAR (STM32_ETHMAC_BASE+STM32_ETH_PTPTSAR_OFFSET)
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#define STM32_ETH_PTPTTHR (STM32_ETHMAC_BASE+STM32_ETH_PTPTTHR_OFFSET)
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#define STM32_ETH_PTPTTLR (STM32_ETHMAC_BASE+STM32_ETH_PTPTTLR_OFFSET)
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#define STM32_ETH_PTPTSSR (STM32_ETHMAC_BASE+STM32_ETH_PTPTSSR_OFFSET)
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/* DMA Registers */
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#define STM32_ETH_DMABMR (STM32_ETHERNET_BASE+STM32_ETH_DMABMR_OFFSET)
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#define STM32_ETH_DMATPDR (STM32_ETHERNET_BASE+STM32_ETH_DMATPDR_OFFSET)
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#define STM32_ETH_DMARPDR (STM32_ETHERNET_BASE+STM32_ETH_DMARPDR_OFFSET)
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#define STM32_ETH_DMARDLAR (STM32_ETHERNET_BASE+STM32_ETH_DMARDLAR_OFFSET)
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#define STM32_ETH_DMATDLAR (STM32_ETHERNET_BASE+STM32_ETH_DMATDLAR_OFFSET)
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#define STM32_ETH_DMASR (STM32_ETHERNET_BASE+STM32_ETH_DMASR_OFFSET)
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#define STM32_ETH_DMAOMR (STM32_ETHERNET_BASE+STM32_ETH_DMAOMR_OFFSET)
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#define STM32_ETH_DMAIER (STM32_ETHERNET_BASE+STM32_ETH_DMAIER_OFFSET)
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#define STM32_ETH_DMAMFBOC (STM32_ETHERNET_BASE+STM32_ETH_DMAMFBOC_OFFSET)
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#define STM32_ETH_DMARSWTR (STM32_ETHERNET_BASE+STM32_ETH_DMARSWTR_OFFSET)
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#define STM32_ETH_DMACHTDR (STM32_ETHERNET_BASE+STM32_ETH_DMACHTDR_OFFSET)
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#define STM32_ETH_DMACHRDR (STM32_ETHERNET_BASE+STM32_ETH_DMACHRDR_OFFSET)
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#define STM32_ETH_DMACHTBAR (STM32_ETHERNET_BASE+STM32_ETH_DMACHTBAR_OFFSET)
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#define STM32_ETH_DMACHRBAR (STM32_ETHERNET_BASE+STM32_ETH_DMACHRBAR_OFFSET)
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#define STM32_ETH_DMABMR (STM32_ETHMAC_BASE+STM32_ETH_DMABMR_OFFSET)
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#define STM32_ETH_DMATPDR (STM32_ETHMAC_BASE+STM32_ETH_DMATPDR_OFFSET)
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#define STM32_ETH_DMARPDR (STM32_ETHMAC_BASE+STM32_ETH_DMARPDR_OFFSET)
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#define STM32_ETH_DMARDLAR (STM32_ETHMAC_BASE+STM32_ETH_DMARDLAR_OFFSET)
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#define STM32_ETH_DMATDLAR (STM32_ETHMAC_BASE+STM32_ETH_DMATDLAR_OFFSET)
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#define STM32_ETH_DMASR (STM32_ETHMAC_BASE+STM32_ETH_DMASR_OFFSET)
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#define STM32_ETH_DMAOMR (STM32_ETHMAC_BASE+STM32_ETH_DMAOMR_OFFSET)
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#define STM32_ETH_DMAIER (STM32_ETHMAC_BASE+STM32_ETH_DMAIER_OFFSET)
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#define STM32_ETH_DMAMFBOC (STM32_ETHMAC_BASE+STM32_ETH_DMAMFBOC_OFFSET)
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#define STM32_ETH_DMARSWTR (STM32_ETHMAC_BASE+STM32_ETH_DMARSWTR_OFFSET)
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#define STM32_ETH_DMACHTDR (STM32_ETHMAC_BASE+STM32_ETH_DMACHTDR_OFFSET)
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#define STM32_ETH_DMACHRDR (STM32_ETHMAC_BASE+STM32_ETH_DMACHRDR_OFFSET)
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#define STM32_ETH_DMACHTBAR (STM32_ETHMAC_BASE+STM32_ETH_DMACHTBAR_OFFSET)
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#define STM32_ETH_DMACHRBAR (STM32_ETHMAC_BASE+STM32_ETH_DMACHRBAR_OFFSET)
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/* Register Bit-Field Definitions *******************************************************************/
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/* MAC Registers */
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@ -67,9 +67,10 @@
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#include "up_internal.h"
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#include "chip.h"
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#include "chip/stm32_syscfg.h"
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#include "chip/stm32_pinmap.h"
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#include "stm32_gpio.h"
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#include "stm32_rcc.h"
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#include "chip/stm32_syscfg.h"
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#include "stm32_ethernet.h"
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#include <arch/board/board.h>
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@ -475,7 +476,7 @@
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#define DMABMR_CLEAR_MASK \
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(ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \
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ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \
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ETH_DMABMR_PBL_MASK | ETH_DMABMR_PM_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \
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ETH_DMABMR_USP | ETH_DMABMR_FPM | ETH_DMABMR_AAB | ETH_DMABMR_MB)
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/* The following bits are set or left zero unconditionally in all modes.
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