From 9bcf27d15baa4532edaa10614f25177acaa4f3c1 Mon Sep 17 00:00:00 2001
From: Gregory Nutt <gnutt@nuttx.org>
Date: Sat, 26 Dec 2015 14:47:54 -0600
Subject: [PATCH] TMS570 is big-endian

---
 arch/arm/Kconfig                |  1 +
 arch/arm/src/armv7-a/arm_head.S | 11 ++++++++++-
 arch/arm/src/armv7-r/arm_head.S | 11 ++++++++++-
 3 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c71310194d..60d291a8c7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -237,6 +237,7 @@ config ARCH_CHIP_STR71X
 
 config ARCH_CHIP_TMS570
 	bool "TI TMS570"
+	select ENDIAN_BIG
 	select ARCH_HAVE_LOWVECTORS
 	select ARCH_HAVE_RAMFUNCS
 	select ARMV7R_MEMINIT
diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S
index da3f8d6f2e..5af4f17ddf 100644
--- a/arch/arm/src/armv7-a/arm_head.S
+++ b/arch/arm/src/armv7-a/arm_head.S
@@ -410,7 +410,7 @@ __start:
 	 *                      replacement strategy.
 	 *   SCTLR_HA   Bit 17: Not supported by A5
 	 *
-	 *   SCTLR_EE   Bit 25: Little endian (reset value).
+	 *   SCTLR_EE   Bit 25: 0=Little endian (reset value).
 	 *   SCTLR_TRE  Bit 28: No memory region remapping (reset value)
 	 *   SCTLR_AFE  Bit 29: Full, legacy access permissions behavior (reset value).
 	 *   SCTLR_TE   Bit 30: All exceptions handled in ARM state (reset value).
@@ -477,6 +477,15 @@ __start:
 	orr		r0, r0, #(SCTLR_A)
 #endif
 
+#ifdef CONFIG_ENDIAN_BIG
+	/* Big endian mode
+	 *
+	 *   SCTLR_EE       Bit 25: 1=Big endian.
+	 */
+
+	orr		r0, r0, #(SCTLR_EE)
+#endif
+
 #ifdef CPU_AFE_ENABLE
 	/* AP[0:2] Permissions model
 	 *
diff --git a/arch/arm/src/armv7-r/arm_head.S b/arch/arm/src/armv7-r/arm_head.S
index a4bff79074..755c700f9b 100644
--- a/arch/arm/src/armv7-r/arm_head.S
+++ b/arch/arm/src/armv7-r/arm_head.S
@@ -217,7 +217,7 @@ __start:
 	 *   SCTLR_U        Bit 22: Unaligned access model (always one)
 	 *
 	 *   SCTLR_VE       Bit 24: Interrupt Vectors Enable bit
-	 *   SCTLR_EE       Bit 25: Little endian.
+	 *   SCTLR_EE       Bit 25: 0=Little endian.
 	 *   SCTLR_NMFI     Bit 27: Non-maskable FIQ (NMFI) support
 	 *   SCTLR_TE       Bit 30: All exceptions handled in ARM state.
 	 *   SCTLR_IE       Bit 31: Instruction endian-ness.
@@ -322,6 +322,15 @@ __start:
 	orr		r0, r0, #(SCTLR_VE)
 #endif
 
+#ifdef CONFIG_ENDIAN_BIG
+	/* Big endian mode
+	 *
+	 *   SCTLR_EE       Bit 25: 1=Big endian.
+	 */
+
+	orr		r0, r0, #(SCTLR_EE)
+#endif
+
 #ifdef CPU_NONMASKABLE_FIQ
 	/* Non-maskable FIQ support
 	 *