From 9967989b02d080ae8dab3ee362a69d56b66f0ef9 Mon Sep 17 00:00:00 2001 From: simbit18 <101105604+simbit18@users.noreply.github.com> Date: Mon, 8 Apr 2024 16:21:13 +0200 Subject: [PATCH] Fix Kconfig style Remove spaces from Kconfig files Remove TABs Add comments --- arch/arm/src/imxrt/Kconfig | 2 +- arch/arm/src/sama5/Kconfig | 10 +++--- arch/risc-v/Kconfig | 56 ++++++++++++++++----------------- arch/x86_64/Kconfig | 4 +-- arch/xtensa/src/esp32s3/Kconfig | 4 +-- boards/Kconfig | 4 +-- drivers/mtd/Kconfig | 6 ++-- 7 files changed, 43 insertions(+), 43 deletions(-) diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig index 5de5cb6a44..e6ccf5b44e 100644 --- a/arch/arm/src/imxrt/Kconfig +++ b/arch/arm/src/imxrt/Kconfig @@ -2613,7 +2613,7 @@ config IMXRT_SRAM_HEAPOFFSET Used to reserve memory at the beginning of SRAM for, as an example, a framebuffer. -endmenu # i.MX RT Heap Configuration +endmenu # i.MX RT Heap Configuration config IMXRT_FLEXRAM_PARTITION bool "Set FlexRAM Paritioning" diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig index 09f6ea1676..611baba875 100644 --- a/arch/arm/src/sama5/Kconfig +++ b/arch/arm/src/sama5/Kconfig @@ -1108,16 +1108,16 @@ choice default SAMA5D2_CLASSD_PWM_TRAILING ---help--- TRAILING EDGE: The signal is single-ended. - If bit NON_OVERLAP is cleared, the signal is sent to + If bit NON_OVERLAP is cleared, the signal is sent to CLASSD_L0 and CLASSD_R0. If bit NON_OVERLAP is set, the signal is sent to CLASSD_L0/L1 and CLASSD_R0/R1. UNIFORM: The signal is differential. - If bit NON_OVERLAP is cleared, the signal is sent to + If bit NON_OVERLAP is cleared, the signal is sent to CLASSD_L0/L2 and CLASSD_R0/R2. - If bit NON_OVERLAP is set, the signal is sent to + If bit NON_OVERLAP is set, the signal is sent to CLASSD_L0/L1/L2/L3 and CLASSD_R0/R1/R2/R3. config SAMA5D2_CLASSD_PWM_TRAILING @@ -1245,8 +1245,8 @@ config SAMA5D2_CLASSD_MONO default 0 ---help--- Disabled. The signal is sent stereo to the left and right channels. - Enabled. The same signal is sent on both left and right channels. - The sent signal is defined by the MONOMODE field value. + Enabled. The same signal is sent on both left and right channels. + The sent signal is defined by the MONOMODE field value. choice prompt "Mono Mode Selection (MONOMODE)" diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig index 50a4d1547e..6a6d3f9a39 100644 --- a/arch/risc-v/Kconfig +++ b/arch/risc-v/Kconfig @@ -328,7 +328,7 @@ config ARCH_CHIP_RISCV_CUSTOM ---help--- Select this option if there is no directory for the chip under arch/risc-v/src/. -endchoice +endchoice # RISC-V chip selection config ARCH_RV32 bool @@ -389,35 +389,35 @@ config ARCH_RV_ISA_VENDOR_EXTENSIONS config ARCH_RV_MMIO_BITS int # special cases - default 32 if ARCH_CHIP_K230 + default 32 if ARCH_CHIP_K230 # general fallbacks - default 32 if ARCH_RV32 - default 64 if ARCH_RV64 + default 32 if ARCH_RV32 + default 64 if ARCH_RV64 config ARCH_FAMILY string - default "rv32" if ARCH_RV32 - default "rv64" if ARCH_RV64 + default "rv32" if ARCH_RV32 + default "rv64" if ARCH_RV64 config ARCH_CHIP string - default "fe310" if ARCH_CHIP_FE310 - default "k210" if ARCH_CHIP_K210 - default "litex" if ARCH_CHIP_LITEX - default "bl602" if ARCH_CHIP_BL602 - default "esp32c3-legacy" if ARCH_CHIP_ESP32C3 - default "esp32c3" if ARCH_CHIP_ESP32C3_GENERIC - default "esp32c6" if ARCH_CHIP_ESP32C6 - default "esp32h2" if ARCH_CHIP_ESP32H2 - default "c906" if ARCH_CHIP_C906 - default "mpfs" if ARCH_CHIP_MPFS - default "rv32m1" if ARCH_CHIP_RV32M1 - default "qemu-rv" if ARCH_CHIP_QEMU_RV - default "hpm6000" if ARCH_CHIP_HPM6000 - default "hpm6750" if ARCH_CHIP_HPM6750 - default "jh7110" if ARCH_CHIP_JH7110 - default "bl808" if ARCH_CHIP_BL808 - default "k230" if ARCH_CHIP_K230 + default "fe310" if ARCH_CHIP_FE310 + default "k210" if ARCH_CHIP_K210 + default "litex" if ARCH_CHIP_LITEX + default "bl602" if ARCH_CHIP_BL602 + default "esp32c3-legacy" if ARCH_CHIP_ESP32C3 + default "esp32c3" if ARCH_CHIP_ESP32C3_GENERIC + default "esp32c6" if ARCH_CHIP_ESP32C6 + default "esp32h2" if ARCH_CHIP_ESP32H2 + default "c906" if ARCH_CHIP_C906 + default "mpfs" if ARCH_CHIP_MPFS + default "rv32m1" if ARCH_CHIP_RV32M1 + default "qemu-rv" if ARCH_CHIP_QEMU_RV + default "hpm6000" if ARCH_CHIP_HPM6000 + default "hpm6750" if ARCH_CHIP_HPM6750 + default "jh7110" if ARCH_CHIP_JH7110 + default "bl808" if ARCH_CHIP_BL808 + default "k230" if ARCH_CHIP_K230 config ARCH_RISCV_INTXCPT_EXTENSIONS bool "RISC-V Integer Context Extensions" @@ -498,7 +498,7 @@ config RISCV_TOOLCHAIN_GNU_RV32 This option should work for any modern GNU toolchain (GCC 5.2 or newer) configured for riscv32-unknown-elf. -endchoice +endchoice # Toolchain Selection config RISCV_SEMIHOSTING_HOSTFS bool "Semihosting HostFS" @@ -517,7 +517,7 @@ config RISCV_SEMIHOSTING_HOSTFS_CACHE_COHERENCE ---help--- Flush & Invalidte cache before & after bkpt instruction. -endif +endif # RISCV_SEMIHOSTING_HOSTFS if ARCH_CHIP_LITEX @@ -538,9 +538,9 @@ config LITEX_CORE_VEXRISCV_SMP select ARCH_HAVE_S_MODE select ARCH_HAVE_ELF_EXECUTABLE -endchoice +endchoice # LITEX Core Selection -endif +endif # ARCH_CHIP_LITEX source "arch/risc-v/src/opensbi/Kconfig" source "arch/risc-v/src/nuttsbi/Kconfig" @@ -596,4 +596,4 @@ endif if ARCH_CHIP_K230 source "arch/risc-v/src/k230/Kconfig" endif -endif +endif # ARCH_RISCV diff --git a/arch/x86_64/Kconfig b/arch/x86_64/Kconfig index 7a12074667..c2da844c5c 100644 --- a/arch/x86_64/Kconfig +++ b/arch/x86_64/Kconfig @@ -107,8 +107,8 @@ config MULTBOOT2_FB_TERM bool "Multiboot2 framebuffer terminal" default n depends on NXFONTS - ---help--- - Enable a framebuffer terminal for early debug printing + ---help--- + Enable a framebuffer terminal for early debug printing endif # ARCH_MULTIBOOT2 diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig index c147e2c15e..11067fb97f 100644 --- a/arch/xtensa/src/esp32s3/Kconfig +++ b/arch/xtensa/src/esp32s3/Kconfig @@ -1884,10 +1884,10 @@ config ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK can do SPI Flash read/write/erase/map/unmap. Otherwise, it may cause exception, the root cause is as following: 1. When operating SPI flash, cache is also disable, - then software can't access PSRAM by data cache. + then software can't access PSRAM by data cache. 2. SPI flash read/write/erase functions have instruction like stack-pop and stack-push which may use stack buffer which is - PSRAM space or load/store temp variables which locate in PSRAM space too. + PSRAM space or load/store temp variables which locate in PSRAM space too. 3. Once operation in step 2 triggers, CPU will trigger exception. So related SPI flash functions should be sent and run in tasks which use SRAM as task stack. diff --git a/boards/Kconfig b/boards/Kconfig index 57d0076507..5c96c79f7a 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -3174,7 +3174,7 @@ config ARCH_BOARD default "esp32s3-box" if ARCH_BOARD_ESP32S3_BOX default "esp32c6-devkitc" if ARCH_BOARD_ESP32C6_DEVKITC default "esp32c6-devkitm" if ARCH_BOARD_ESP32C6_DEVKITM - default "esp32h2-devkit" if ARCH_BOARD_ESP32H2_DEVKIT + default "esp32h2-devkit" if ARCH_BOARD_ESP32H2_DEVKIT default "et-stm32-stamp" if ARCH_BOARD_ET_STM32_STAMP default "tlsr8278adk80d" if ARCH_BOARD_TLSR8278ADK80D default "ez80f910200kitg" if ARCH_BOARD_EZ80F910200KITG @@ -3443,7 +3443,7 @@ config ARCH_BOARD default "xx3803" if ARCH_BOARD_XX3803 default "xx3823" if ARCH_BOARD_XX3823 default "s698pm-dkit" if ARCH_BOARD_S698PM_DKIT - default "hpm6360evk" if ARCH_BOARD_HPM6360EVK + default "hpm6360evk" if ARCH_BOARD_HPM6360EVK default "hpm6750evk2" if ARCH_BOARD_HPM6750EVK2 default "at32f437-mini" if ARCH_BOARD_AT32F437_MINI diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 5b16be665a..ac27e511f4 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -496,7 +496,7 @@ config AT24XX_FREQUENCY int "AT24xx I2C bus frequency" default 100000 ---help--- - Set the I2C frequency to use when accessing the AT24CXX EEPROM. + Set the I2C frequency to use when accessing the AT24CXX EEPROM. This value must represent a valid I2C speed (normally less than 400.000) or the driver might fail. @@ -509,7 +509,7 @@ config MTD_AT25EE select MTD_BYTE_WRITE ---help--- Build support for SPI-based AT25xx type EEPROMs. MTD on EEPROM can - perform poorly, so it is possible only usable if the EEPROM has a + perform poorly, so it is possible only usable if the EEPROM has a clock speed 10MHz or higher. EEPROMs that use the same commands as the 25AA160 should work OK. @@ -525,7 +525,7 @@ choice pages so that the file system block size is, say, 128, 256 or 512 bytes. - In any event, the block size *must* be an even multiple of the + In any event, the block size *must* be an even multiple of the number of pages and, often, needs to be a factor 2. This is up to the user to check!