From 94fb8f4d2a3f03698d7103acd437eb2383b7041e Mon Sep 17 00:00:00 2001 From: Abdelatif Guettouche Date: Mon, 31 Jan 2022 13:16:12 +0100 Subject: [PATCH] esp32s3_rom.ld: Lowercase cache related function to comply with nxstyle. Signed-off-by: Abdelatif Guettouche --- .../esp32s2-saola-1/scripts/esp32s2_rom.ld | 24 ++++++++++++++++++- .../esp32s3-devkit/scripts/esp32s3_rom.ld | 6 ++--- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld index e430f33a93..3290eb3b6f 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld @@ -45,7 +45,7 @@ PROVIDE ( Cache_Get_Mode = 0x40017ff0 ); PROVIDE ( Cache_Get_Virtual_Addr = 0x40019210 ); PROVIDE ( cache_ibus_mmu_set = 0x40018df4 ); PROVIDE ( Cache_ICache_Preload_Done = 0x4001859c ); -PROVIDE ( Cache_Invalidate_Addr = 0x400182e4 ); +PROVIDE ( cache_invalidate_addr = 0x400182e4 ); PROVIDE ( Cache_Invalidate_DCache_All = 0x4001842c ); PROVIDE ( Cache_Invalidate_DCache_Items = 0x40018208 ); PROVIDE ( cache_invalidate_icache_all = 0x40018420 ); @@ -816,6 +816,28 @@ PROVIDE ( strncpy = 0x40007f20 ); PROVIDE ( strlen = 0x40007e08 ); PROVIDE ( strnlen = 0x4001ae9c ); +/* Rename the SPI Flash data and functions. */ + +PROVIDE ( g_rom_spiflash_dummy_len_plus = dummy_len_plus); +PROVIDE ( g_spiflash_chip = SPI_flashchip_data ); +PROVIDE ( spi_flash_config_param = SPIParamCfg ); +PROVIDE ( spi_flash_read = SPIRead ); +PROVIDE ( spi_flash_read_status = SPI_read_status ); +PROVIDE ( spi_flash_read_statushigh = SPI_read_status_high ); +PROVIDE ( spi_flash_read_user_cmd = SPI_user_command_read ); +PROVIDE ( spi_flash_write = SPIWrite ); +PROVIDE ( spi_flash_write_encrypted_disable = SPI_Write_Encrypt_Disable ); +PROVIDE ( spi_flash_write_encrypted_enable = SPI_Write_Encrypt_Enable ); +PROVIDE ( spi_flash_config_clk = SPIClkConfig ); +PROVIDE ( spi_flash_select_qio_pins = SelectSpiQIO ); +PROVIDE ( spi_flash_unlock = SPIUnlock ); +PROVIDE ( spi_flash_erase_sector = SPIEraseSector ); +PROVIDE ( spi_flash_erase_block = SPIEraseBlock ); +PROVIDE ( spi_flash_wait_idle = SPI_Wait_Idle ); +PROVIDE ( spi_flash_config_readmode = SPIReadModeCnfig ); +PROVIDE ( spi_flash_erase_block = SPIEraseBlock ); +PROVIDE ( spi_flash_write_encrypted = SPI_Encrypt_Write ); + /* Unlike other ROM functions which are exported using PROVIDE, which declares weak symbols, * these libgcc functions are exported using assignment, which declare strong symbols. * This is done so that ROM functions are always used instead of the ones provided by libgcc.a. diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_rom.ld b/boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_rom.ld index 7065096316..3b7a964e04 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_rom.ld +++ b/boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_rom.ld @@ -388,7 +388,7 @@ PROVIDE( Cache_Invalidate_DCache_Items = 0x40001680 ); PROVIDE( Cache_Clean_Items = 0x4000168c ); PROVIDE( Cache_WriteBack_Items = 0x40001698 ); PROVIDE( Cache_Op_Addr = 0x400016a4 ); -PROVIDE( Cache_Invalidate_Addr = 0x400016b0 ); +PROVIDE( cache_invalidate_addr = 0x400016b0 ); PROVIDE( Cache_Clean_Addr = 0x400016bc ); PROVIDE( Cache_WriteBack_Addr = 0x400016c8 ); PROVIDE( Cache_Invalidate_ICache_All = 0x400016d4 ); @@ -429,8 +429,8 @@ PROVIDE( Cache_Disable_ICache = 0x4000186c ); PROVIDE( Cache_Enable_ICache = 0x40001878 ); PROVIDE( Cache_Disable_DCache = 0x40001884 ); PROVIDE( Cache_Enable_DCache = 0x40001890 ); -PROVIDE( Cache_Suspend_ICache = 0x4000189c ); -PROVIDE( Cache_Resume_ICache = 0x400018a8 ); +PROVIDE( cache_suspend_icache = 0x4000189c ); +PROVIDE( cache_resume_icache = 0x400018a8 ); PROVIDE( cache_suspend_dcache = 0x400018b4 ); PROVIDE( cache_resume_dcache = 0x400018c0 ); PROVIDE( Cache_Occupy_Items = 0x400018cc );