Tiva Ethernet: Update DMA BUSMODE settings based on TI example code
This commit is contained in:
Gregory Nutt
parent
339f71a315
commit
9461b88edc
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@ -509,39 +509,69 @@
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(EMAC_DMABUSMOD_SWR | EMAC_DMABUSMOD_DA | EMAC_DMABUSMOD_DSL_MASK | \
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EMAC_DMABUSMOD_ATDS | EMAC_DMABUSMOD_PBL_MASK | EMAC_DMABUSMOD_PR_MASK | \
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EMAC_DMABUSMOD_FB | EMAC_DMABUSMOD_RPBL_MASK | EMAC_DMABUSMOD_USP | \
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EMAC_DMABUSMOD_8XPBL | EMAC_DMABUSMOD_AAL | EMAC_DMABUSMOD_MB)
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EMAC_DMABUSMOD_8XPBL | EMAC_DMABUSMOD_AAL | EMAC_DMABUSMOD_MB |\
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EMAC_DMABUSMOD_TXPR | EMAC_DMABUSMOD_RIB)
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/* The following bits are set or left zero unconditionally in all modes.
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*
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*
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* EMAC_DMABUSMOD_SWR Software reset 0 (no reset)
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* EMAC_DMABUSMOD_DA DMA Arbitration 0 (round robin)
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* EMAC_DMABUSMOD_DA DMA Arbitration 1 (fixed priority)
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* EMAC_DMABUSMOD_DSL Descriptor skip length 0
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* EMAC_DMABUSMOD_ATDS Enhanced descriptor format enable Depends on CONFIG_TIVA_EMAC_ENHANCEDDESC
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* EMAC_DMABUSMOD_PBL Programmable burst length 32 beats
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* EMAC_DMABUSMOD_PR RX TX priority ratio 2:1
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* EMAC_DMABUSMOD_FB Fixed burst 1 (enabled)
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* EMAC_DMABUSMOD_RPBL RX DMA programmable burst length 32 beats
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* EMAC_DMABUSMOD_USP Use separate PBL 1 (enabled)
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* EMAC_DMABUSMOD_8XPBL 8x programmable burst length mode 0 (disabled)
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* EMAC_DMABUSMOD_AAL Address-aligned beats 1 (enabled)
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* EMAC_DMABUSMOD_MB Mixed burst 0 (disabled, F2/F4 only)
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* EMAC_DMABUSMOD_PBL Programmable burst length Depends on EMAC_DMA_RXBURST
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* EMAC_DMABUSMOD_PR RX TX priority ratio 0 1:1
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* EMAC_DMABUSMOD_FB Fixed burst 0 (disabled)
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* EMAC_DMABUSMOD_RPBL RX DMA programmable burst length Depends on EMAC_DMA_TXBURST
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* EMAC_DMABUSMOD_USP Use separate PBL Depends on EMAC_DMA_RX/TXBURST
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* EMAC_DMABUSMOD_8XPBL 8x programmable burst length mode Depends on EMAC_DMA_RX/TXBURST
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* EMAC_DMABUSMOD_AAL Address-aligned beats 0 (disabled)
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* EMAC_DMABUSMOD_MB Mixed burst 1 (enabled)
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* EMAC_DMABUSMOD_TXPR Transmit Priority 0 (RX DMA has priority over TX)
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* EMAC_DMABUSMOD_RIB Rebuild Burst 0
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*/
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#ifdef CONFIG_TIVA_EMAC_ENHANCEDDESC
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# define DMABUSMOD_SET_MASK \
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(EMAC_DMABUSMOD_DSL(0) | EMAC_DMABUSMOD_PBL(32) | EMAC_DMABUSMOD_ATDS | \
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EMAC_DMABUSMOD_PR_2TO1 | EMAC_DMABUSMOD_FB | EMAC_DMABUSMOD_RPBL(32) | \
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EMAC_DMABUSMOD_USP | EMAC_DMABUSMOD_AAL)
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#define EMAC_DMA_RXBURST 4
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#define EMAC_DMA_TXBURST 4
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#if EMAC_DMA_RXBURST > 32 || EMAC_DMA_TXBURST > 32
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# define __EMAC_DMABUSMOD_8XPBL 0
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# define __EMAC_DMA_RXBURST EMAC_DMA_RXBURST
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# define __EMAC_DMA_TXBURST EMAC_DMA_TXBURST
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#else
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# define DMABUSMOD_SET_MASK \
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(EMAC_DMABUSMOD_DSL(0) | EMAC_DMABUSMOD_PBL(32) | EMAC_DMABUSMOD_PR_2TO1 | \
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EMAC_DMABUSMOD_FB | EMAC_DMABUSMOD_RPBL(32) | EMAC_DMABUSMOD_USP | \
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EMAC_DMABUSMOD_AAL)
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/* Divide both burst lengths by 8 and set the 8X burst length multiplier */
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# define __EMAC_DMABUSMOD_8XPBL EMAC_DMABUSMOD_8XPBL
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# define __EMAC_DMA_RXBURST (EMAC_DMA_RXBURST >> 3)
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# define __EMAC_DMA_TXBURST (EMAC_DMA_TXBURST >> 3)
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#endif
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#define __EMAC_DMABUSMOD_PBL EMAC_DMABUSMOD_PBL(__EMAC_DMA_RXBURST)
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/* Are the receive and transmit burst lengths the same? */
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#if __EMAC_DMA_RXBURST == __EMAC_DMA_TXBURST
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/* Yes.. Set up to use a single burst length */
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# define __EMAC_DMABUSMOD_USP 0
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# define __EMAC_DMABUSMOD_RPBL 0
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#else
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/* No.. Use separate burst lengths for each */
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# define __EMAC_DMABUSMOD_USP EMAC_DMABUSMOD_USP
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# define __EMAC_DMABUSMOD_RPBL EMAC_DMABUSMOD_RPBL(__EMAC_DMA_TXBURST)
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#endif
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#ifdef CONFIG_TIVA_EMAC_ENHANCEDDESC
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# define __EMAC_DMABUSMOD_ATDS EMAC_DMABUSMOD_ATDS
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#else
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# define __EMAC_DMABUSMOD_ATDS 0
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#endif
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#define DMABUSMOD_SET_MASK \
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(EMAC_DMABUSMOD_DA | EMAC_DMABUSMOD_DSL(0) | __EMAC_DMABUSMOD_ATDS | \
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__EMAC_DMABUSMOD_PBL | __EMAC_DMABUSMOD_RPBL | __EMAC_DMABUSMOD_USP | \
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__EMAC_DMABUSMOD_8XPBL | EMAC_DMABUSMOD_MB)
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/* Interrupt bit sets *******************************************************/
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/* All interrupts in the normal and abnormal interrupt summary. Early transmit
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* interrupt (ETI) is excluded from the abnormal set because it causes too
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@ -715,6 +745,7 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv);
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/* MAC/DMA Initialization */
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static void tiva_phy_hold(FAR struct tiva_ethmac_s *priv);
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static inline void tiva_phy_release(FAR struct tiva_ethmac_s *priv);
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static void tiva_phy_configure(FAR struct tiva_ethmac_s *priv);
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static inline void tiva_phy_initialize(FAR struct tiva_ethmac_s *priv);
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@ -722,7 +753,7 @@ static void tiva_ethreset(FAR struct tiva_ethmac_s *priv);
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static int tiva_macconfig(FAR struct tiva_ethmac_s *priv);
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static void tiva_macaddress(FAR struct tiva_ethmac_s *priv);
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static int tiva_macenable(FAR struct tiva_ethmac_s *priv);
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static int tiva_ethconfig(FAR struct tiva_ethmac_s *priv);
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static int tive_emac_configure(FAR struct tiva_ethmac_s *priv);
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/****************************************************************************
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* Private Functions
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@ -2318,7 +2349,7 @@ static int tiva_ifup(struct net_driver_s *dev)
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/* Configure the Ethernet interface for DMA operation. */
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ret = tiva_ethconfig(priv);
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ret = tive_emac_configure(priv);
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if (ret < 0)
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{
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return ret;
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@ -3011,6 +3042,10 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
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priv->mbps100 = 0;
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priv->fduplex = 0;
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/* Allow the PHY to transmit on the line */
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tiva_phy_release(priv);
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/* Setup up PHY clocking by setting the SR field in the MIIADDR register */
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regval = tiva_getreg(TIVA_EMAC_MIIADDR);
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@ -3185,7 +3220,7 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
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* Function: tiva_phy_hold
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*
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* Description:
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* Reset the PHY
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* Hold the Ethernet PHY from transmitting energy
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*
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* Parameters:
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* priv - A reference to the private driver state structure
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@ -3197,7 +3232,7 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
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*
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****************************************************************************/
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static inline void tiva_phy_hold(FAR struct tiva_ethmac_s *priv)
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static void tiva_phy_hold(FAR struct tiva_ethmac_s *priv)
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{
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uint32_t regval;
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@ -3210,6 +3245,33 @@ static inline void tiva_phy_hold(FAR struct tiva_ethmac_s *priv)
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tiva_putreg(regval, TIVA_EMAC_PC);
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}
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/****************************************************************************
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* Function: tiva_phy_release
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*
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* Description:
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* Release the PHY so that is can transmit energy on the line.
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*
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* Parameters:
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* priv - A reference to the private driver state structure
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*
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* Returned Value:
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* None.
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*
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* Assumptions:
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*
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****************************************************************************/
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static inline void tiva_phy_release(FAR struct tiva_ethmac_s *priv)
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{
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uint32_t regval;
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/* Clear the PHYHOLD bit in the EMACPC register */
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regval = tiva_getreg(TIVA_EMAC_PC);
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regval &= ~EMAC_PC_PHYHOLD;
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tiva_putreg(regval, TIVA_EMAC_PC);
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}
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/****************************************************************************
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* Function: tiva_phy_configure
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*
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@ -3262,12 +3324,7 @@ static void tiva_phy_configure(FAR struct tiva_ethmac_s *priv)
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/* Wait for the reset to complete */
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while (!tiva_ephy_periphrdy())
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{
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}
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/* Delay a bit longer to ensure that the PHY reset has completed. */
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while (!tiva_ephy_periphrdy());
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up_udelay(250);
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#endif
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@ -3324,9 +3381,8 @@ static inline void tiva_phy_initialize(FAR struct tiva_ethmac_s *priv)
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* continuing.
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*/
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while (!tiva_ephy_periphrdy())
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{
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}
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while (!tiva_ephy_periphrdy());
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up_udelay(250);
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/* Enable power to the Ethernet PHY */
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@ -3336,9 +3392,8 @@ static inline void tiva_phy_initialize(FAR struct tiva_ethmac_s *priv)
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* to be accessed.
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*/
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while (!tiva_ephy_periphrdy())
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{
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}
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while (!tiva_ephy_periphrdy());
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up_udelay(250);
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#ifdef CONFIG_TIVA_PHY_INTERNAL
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/* Integrated PHY:
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@ -3506,6 +3561,11 @@ static void tiva_ethreset(FAR struct tiva_ethmac_s *priv)
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regval &= ~SYSCON_SREMAC_R0;
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tiva_putreg(regval, TIVA_SYSCON_SREMAC);
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/* What for the reset to complete */
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while (!tiva_emac_periphrdy());
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up_udelay(250);
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/* Configure the PHY */
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tiva_phy_configure(priv);
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@ -3725,7 +3785,7 @@ static int tiva_macenable(FAR struct tiva_ethmac_s *priv)
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}
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/****************************************************************************
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* Function: tiva_ethconfig
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* Function: tive_emac_configure
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*
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* Description:
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* Configure the Ethernet interface for DMA operation.
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@ -3740,12 +3800,12 @@ static int tiva_macenable(FAR struct tiva_ethmac_s *priv)
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*
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****************************************************************************/
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static int tiva_ethconfig(FAR struct tiva_ethmac_s *priv)
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static int tive_emac_configure(FAR struct tiva_ethmac_s *priv)
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{
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int ret;
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/* NOTE: The Ethernet clocks were initialized early in the boot-up
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* sequence in tiva_rcc.c.
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/* NOTE: The Ethernet clocks were initialized earlier in the start-up
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* sequence.
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*/
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/* Reset the Ethernet block */
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@ -3874,9 +3934,8 @@ int tiva_ethinitialize(int intf)
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* to be accessed.
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*/
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while (!tiva_emac_periphrdy())
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{
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}
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while (!tiva_emac_periphrdy());
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up_udelay(250);
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/* Configure GPIOs to support the internal/eternal PHY */
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