arm64/qemu: The PSCI can be configured with CONFIG_ARM64_PSCI

Signed-off-by: wangming9 <wangming9@xiaomi.com>

arch/arm64/Kconfig

@@ -31,9 +31,9 @@ config ARCH_CHIP_A64
 	select ARCH_CORTEX_A53
 	select ARCH_HAVE_ADDRENV
 	select ARCH_HAVE_RESET
-	select ARCH_HAVE_PSCI
 	select ARCH_HAVE_IRQTRIGGER
 	select ARCH_NEED_ADDRENV_MAPPING
+	select ARM64_HAVE_PSCI
 	---help---
 		Allwinner A64 SoC
 
@@ -42,8 +42,8 @@ config ARCH_CHIP_RK3399
 	select ARCH_CORTEX_A53
 	select ARCH_HAVE_ADDRENV
 	select ARCH_HAVE_RESET
-	select ARCH_HAVE_PSCI
 	select ARCH_NEED_ADDRENV_MAPPING
+	select ARM64_HAVE_PSCI
 	---help---
 		Rockchip RK3399 SoC
 
@@ -51,11 +51,11 @@ config ARCH_CHIP_QEMU
 	bool "QEMU virt platform (ARMv8a)"
 	select ARCH_HAVE_ADDRENV
 	select ARCH_HAVE_IRQTRIGGER
-	select ARCH_HAVE_PSCI
 	select ARCH_NEED_ADDRENV_MAPPING
 	select ARCH_HAVE_POWEROFF
 	select ARCH_HAVE_RESET
 	select ARCH_HAVE_TEXT_HEAP
+	select ARM64_HAVE_PSCI
 	select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF
 	---help---
 		QEMU virt platform (ARMv8a)
@@ -63,7 +63,6 @@ config ARCH_CHIP_QEMU
 config ARCH_CHIP_GOLDFISH
 	bool "goldfish platform (ARMv8a)"
 	select ARCH_CORTEX_A53
-	select ARCH_HAVE_PSCI
 	select ARCH_HAVE_MULTICPU
 	select ARMV8A_HAVE_GICv2
 	select ARCH_HAVE_ADDRENV
@@ -71,6 +70,7 @@ config ARCH_CHIP_GOLDFISH
 	select ARCH_HAVE_POWEROFF
 	select ARCH_HAVE_RESET
 	select ARCH_NEED_ADDRENV_MAPPING
+	select ARM64_HAVE_PSCI
 	select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF
 	---help---
 		Android GoldFish platform for NuttX (ARMv8a),
@@ -118,16 +118,6 @@ config ARCH_ARMV8R
 	default n
 	select ARCH_SINGLE_SECURITY_STATE
 
-config ARCH_HAVE_PSCI
-	bool "ARM PCSI (Power State Coordination Interface) Support"
-	default n
-	---help---
-		This Power State Coordination Interface (PSCI) defines
-		a standard interface for power management. the PCSI need
-		to implement handling firmware at EL2 or EL3. The option
-		maybe not applicable for arm core without PCSI firmware
-		interface implement
-
 config ARCH_SINGLE_SECURITY_STATE
 	bool "ARM Single Security State Support"
 	default n
@@ -261,6 +251,23 @@ config ARCH_CHIP
 	default "imx8"      if ARCH_CHIP_IMX8
 	default "imx9"      if ARCH_CHIP_IMX9
 
+config ARM64_HAVE_PSCI
+	bool "ARM PCSI (Power State Coordination Interface) Support"
+	default n
+	---help---
+		This Power State Coordination Interface (PSCI) defines
+		a standard interface for power management. the PCSI need
+		to implement handling firmware at EL2 or EL3. The option
+		maybe not applicable for arm core without PCSI firmware
+		interface implement
+
+config ARM64_PSCI
+	bool "Enabled PSCI"
+	depends on ARM64_HAVE_PSCI
+	default y
+	---help---
+		See ARM64_HAVE_PSCI for details
+
 config ARM64_HAVE_NEON
 	bool
 	default n

arch/arm64/src/a64/a64_boot.c

@@ -102,7 +102,7 @@ void arm64_chip_boot(void)
 
   arm64_mmu_init(true);
 
-#if defined(CONFIG_SMP) || defined(CONFIG_ARCH_HAVE_PSCI)
+#if defined(CONFIG_ARM64_PSCI)
   arm64_psci_init("smc");
 
 #endif

arch/arm64/src/common/CMakeLists.txt

@@ -63,7 +63,7 @@ if(CONFIG_ARCH_HAVE_MPU)
   list(APPEND SRCS arm64_mpu.c)
 endif()
 
-if(CONFIG_ARCH_HAVE_PSCI)
+if(CONFIG_ARM64_PSCI)
   list(APPEND SRCS arm64_cpu_psci.c arm64_systemreset.c)
 endif()
 

arch/arm64/src/common/Make.defs

@@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_HAVE_MPU),y)
 CMN_CSRCS += arm64_mpu.c
 endif
 
-ifeq ($(CONFIG_ARCH_HAVE_PSCI),y)
+ifeq ($(CONFIG_ARM64_PSCI),y)
 CMN_CSRCS += arm64_cpu_psci.c arm64_systemreset.c
 endif
 

arch/arm64/src/common/arm64_cpustart.c

@@ -178,7 +178,7 @@ static void arm64_start_cpu(int cpu_num, char *stack, int stack_sz,
 
   flush_boot_params();
 
-#ifdef CONFIG_ARCH_HAVE_PSCI
+#ifdef CONFIG_ARM64_PSCI
   if (psci_cpu_on(cpu_mpid, (uint64_t)__start))
     {
       serr("Failed to boot secondary CPU core %d (MPID:%#lx)\n", cpu_num,

arch/arm64/src/fvp-v8r/fvp_boot.c

@@ -194,7 +194,7 @@ void arm64_chip_boot(void)
 
   arm64_mpu_init(true);
 
-#if defined(CONFIG_SMP) && defined(CONFIG_ARCH_HAVE_PCSI)
+#if defined(CONFIG_ARM64_PSCI)
   arm64_psci_init("smc");
 #endif
 

arch/arm64/src/goldfish/goldfish_boot.c

@@ -182,7 +182,7 @@ void arm64_chip_boot(void)
   fdt_register((const char *)0x40000000);
 #endif
 
-#ifdef CONFIG_ARCH_HAVE_PSCI
+#ifdef CONFIG_ARM64_PSCI
   arm64_psci_init("smc");
 #endif
 

arch/arm64/src/imx9/Kconfig

@@ -16,7 +16,7 @@ config ARCH_CHIP_IMX93
 	select ARCH_HAVE_MULTICPU
 	select ARMV8A_HAVE_GICv3
 	select ARCH_CORTEX_A55
-	select ARCH_HAVE_PSCI if !IMX9_BOOTLOADER
+	select ARM64_HAVE_PSCI if !IMX9_BOOTLOADER
 	select ARCH_HAVE_PWM_MULTICHAN
 	select ARCH_HAVE_RESET
 

arch/arm64/src/imx9/imx9_boot.c

@@ -123,7 +123,7 @@ void arm64_chip_boot(void)
   imx9_lowsetup();
 #endif
 
-#if defined(CONFIG_SMP) || defined(CONFIG_ARCH_HAVE_PSCI)
+#if defined(CONFIG_ARM64_PSCI)
   arm64_psci_init("smc");
 #endif
 

arch/arm64/src/qemu/Kconfig

@@ -15,21 +15,21 @@ config ARCH_CHIP_QEMU_A53
 	bool "Qemu virtual Processor (cortex-a53)"
 	select ARCH_HAVE_MULTICPU
 	select ARMV8A_HAVE_GICv3
-	select ARCH_HAVE_PSCI
+	select ARM64_HAVE_PSCI
 	select ARCH_CORTEX_A53
 
 config ARCH_CHIP_QEMU_A57
 	bool "Qemu virtual Processor (cortex-a57)"
 	select ARCH_HAVE_MULTICPU
 	select ARMV8A_HAVE_GICv3
-	select ARCH_HAVE_PCSI
+	select ARM64_HAVE_PSCI
 	select ARCH_CORTEX_A57
 
 config ARCH_CHIP_QEMU_A72
 	bool "Qemu virtual Processor (cortex-a72)"
 	select ARCH_HAVE_MULTICPU
 	select ARMV8A_HAVE_GICv3
-	select ARCH_HAVE_PCSI
+	select ARM64_HAVE_PSCI
 	select ARCH_CORTEX_A72
 
 endchoice # Qemu Chip Selection

arch/arm64/src/qemu/qemu_boot.c

@@ -175,9 +175,9 @@ void arm64_chip_boot(void)
   fdt_register((const char *)0x40000000);
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_QEMU_WITH_HV)
+#if defined(CONFIG_ARCH_CHIP_QEMU_WITH_HV) && defined(CONFIG_ARM64_PSCI)
   arm64_psci_init("hvc");
-#elif defined(CONFIG_ARCH_HAVE_PSCI)
+#elif defined(CONFIG_ARM64_PSCI)
   arm64_psci_init("smc");
 #endif
 

arch/arm64/src/rk3399/rk3399_boot.c

@@ -102,7 +102,7 @@ void arm64_chip_boot(void)
 
   arm64_mmu_init(true);
 
-#if defined(CONFIG_SMP) || defined(CONFIG_ARCH_HAVE_PSCI)
+#if defined(CONFIG_ARM64_PSCI)
   arm64_psci_init("smc");
 
 #endif