diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig
index 75f1c9a1b9..f83ce52586 100644
--- a/arch/arm/src/stm32h7/Kconfig
+++ b/arch/arm/src/stm32h7/Kconfig
@@ -1684,6 +1684,16 @@ config STM32H7_DMACAPABLE
 		Drivers then may use this information to determine if they should
 		attempt the DMA or fall back to a different transfer method.
 
+config STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED
+	bool "Do not disqualify DMA capability based on cache alignment"
+	depends on STM32H7_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH
+	default n
+	---help---
+		This option configures the stm32_dmacapable to not disqualify
+		DMA operations on memory that is not dcache aligned based solely
+		on the starting addresss and byte count.
+		Use this when ALL buffer extents are known to be aligned, but the
+		the count does not use the complete buffer.
 
 menu "Timer Configuration"
 
diff --git a/arch/arm/src/stm32h7/stm32_dma.c b/arch/arm/src/stm32h7/stm32_dma.c
index fbe472661c..62db696278 100644
--- a/arch/arm/src/stm32h7/stm32_dma.c
+++ b/arch/arm/src/stm32h7/stm32_dma.c
@@ -1536,7 +1536,9 @@ static bool stm32_sdma_capable(FAR stm32_dmacfg_t *cfg)
         {
           dmainfo("stm32_dmacapable: dcache unaligned "
                   "maddr:0x%08x mend:0x%08x\n", cfg->maddr, mend);
-          return false;
+#if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED)
+      return false;
+#endif
         }
     }
 #  endif
@@ -2059,7 +2061,9 @@ static bool stm32_bdma_capable(FAR stm32_dmacfg_t *cfg)
     {
       dmainfo("stm32_dmacapable: dcache unaligned maddr:0x%08x "
               "mend:0x%08x\n", cfg->maddr, mend);
+#if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED)
       return false;
+#endif
     }
 #  endif