SAMA5 WDT driver is now functional
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@ -452,7 +452,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
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{
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FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower;
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uint32_t reload;
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uint16_t regval;
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uint32_t regval;
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DEBUGASSERT(priv);
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wdvdbg("Entry: timeout=%d\n", timeout);
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@ -511,9 +511,12 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
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regval |= WDT_MR_WDFIEN;
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#else
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/* Reset (everything) if the watchdog timer expires */
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/* Reset (everything) if the watchdog timer expires.
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*
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* REVISIT: Set WDT_MR_WDRPROC so that only the processor is reset?
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*/
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regval |= WDT_MR_WDFIEN;
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regval |= WDT_MR_WDRSTEN;
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#endif
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#ifdef CONFIG_SAMA5_WDT_DEBUGHALT
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@ -535,6 +538,11 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
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*/
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priv->started = true;
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wdvdbg("Setup: CR: %08x MR: %08x SR: %08x\n",
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sam_getreg(SAM_WDT_CR), sam_getreg(SAM_WDT_MR),
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sam_getreg(SAM_WDT_SR));
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return OK;
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}
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@ -666,7 +674,7 @@ int up_wdginitialize(void)
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* case.
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*/
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DEBUGASSERT((sam_getreg(SAM_WDT_MR) & WDT_MR_WDDIS) != 0);
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DEBUGASSERT((sam_getreg(SAM_WDT_MR) & WDT_MR_WDDIS) == 0);
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/* No clock setup is required. The Watchdog Timer uses the Slow Clock
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* divided by 128 to establish the maximum Watchdog period to be 16 seconds
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