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SAMV7: Costmetic changes to SDRAM logic

This commit is contained in:
Gregory Nutt 2015-03-14 13:58:34 -06:00
parent 3b0615ece8
commit 85b9a7f1a5
1 changed files with 14 additions and 12 deletions
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26
configs/samv71-xult/src/sam_sdram.c
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@ -187,17 +187,17 @@ void sam_sdram_config(void)
* SDRAMC_CR_TXSR(13) 70 ns min Exit self-refresh to active time
*/
regval = SDRAMC_CR_NC_COL8 | /* 8 column bits */
SDRAMC_CR_NR_ROW11 | /* 11 row bits */
SDRAMC_CR_NB_BANK2 | /* 2 banks */
SDRAMC_CR_CAS_LATENCY3 | /* 3 cycle CAS latency */
SDRAMC_CR_DBW | /* 16 bit */
SDRAMC_CR_TWR(4) | /* 4 cycle write recovery delay */
SDRAMC_CR_TRCTRFC(11) | /* 63 ns min */
SDRAMC_CR_TRP(5) | /* 21 ns min Command period (PRE to ACT) */
SDRAMC_CR_TRCD(5) | /* 21 ns min Active Command to read/Write Command delay time */
SDRAMC_CR_TRAS(8) | /* 42 ns min Command period (ACT to PRE) */
SDRAMC_CR_TXSR(13); /* 70 ns min Exit self-refresh to active time */
regval = SDRAMC_CR_NC_COL8 | /* 8 column bits */
SDRAMC_CR_NR_ROW11 | /* 11 row bits */
SDRAMC_CR_NB_BANK2 | /* 2 banks */
SDRAMC_CR_CAS_LATENCY3 | /* 3 cycle CAS latency */
SDRAMC_CR_DBW | /* 16 bit */
SDRAMC_CR_TWR(4) | /* 4 cycle write recovery delay */
SDRAMC_CR_TRCTRFC(11) | /* 63 ns min */
SDRAMC_CR_TRP(5) | /* 21 ns min Command period (PRE to ACT) */
SDRAMC_CR_TRCD(5) | /* 21 ns min Active Command to read/Write Command delay time */
SDRAMC_CR_TRAS(8) | /* 42 ns min Command period (ACT to PRE) */
SDRAMC_CR_TXSR(13); /* 70 ns min Exit self-refresh to active time */
putreg32(regval, SAM_SDRAMC_CR);
@ -206,6 +206,8 @@ void sam_sdram_config(void)
* the Low Power Register.
*/
putreg32(0, SAM_SDRAMC_LPR);
/* 3. The SDRAM memory type must be set in the Memory Device Register.*/
putreg32(SDRAMC_MDR_SDRAM, SAM_SDRAMC_MDR);
@ -237,7 +239,7 @@ void sam_sdram_config(void)
* any SDRAM location eight times.
*/
for (i = 0 ; i< 8; i++)
for (i = 0 ; i < 8; i++)
{
putreg32(SDRAMC_MR_MODE_AUTOREFRESH, SAM_SDRAMC_MR);
*psdram = 0;