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xtensa/esp32s2: Fix some wrong definitions related to IRQ management 

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Gustavo Henrique Nihei 2022-01-12 16:23:07 -03:00 committed by Abdelatif Guettouche
parent 0fc613f0b3
commit 80436dd7be
2 changed files with 14 additions and 16 deletions
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22
arch/xtensa/include/esp32s2/irq.h
View File

@ -250,8 +250,8 @@
#define ESP32S2_IRQ_INT_FROM_CPU2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU2)
#define ESP32S2_IRQ_INT_FROM_CPU3 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU3)
#define ESP32_IRQ_SREG0 ESP32S2_IRQ_MAC
#define ESP32_NIRQS_SREG0 32
#define ESP32S2_IRQ_SREG0 ESP32S2_IRQ_MAC
#define ESP32S2_NIRQS_SREG0 32
/* PRO_INTR_STATUS_REG_1 */
@ -328,15 +328,11 @@
#define ESP32S2_IRQ_CPU_PERI_ERR (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CPU_PERI_ERR)
#define ESP32S2_IRQ_APB_PERI_ERE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_APB_PERI_ERR)
#define ESP32S2_IRQ_DCACHE_SYNC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DCACHE_SYNC)
#define ESP32S2_IRQ_ICACHE_SYNC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_ICACHE_SYNC)
#define ESP32S2_IRQ_SREG2 ESP32S2_IRQ_TG_WDT_EDGE
#define ESP32S2_NIRQS_SREG2 32
/* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */
#define ESP32S2_IRQ_SREG2 ESP32S2_IRQ_TG1_WDT_EDGE
#define ESP32S2_NIRQS_SREG2 5
#define ESP32S2_NIRQS_SREG2 31
#define ESP32S2_NIRQ_PERIPH ESP32S2_NPERIPHERALS
@ -417,7 +413,7 @@
#define ESP32S2_CPUINT_LEVELPERIPH_20 31
#define ESP32S2_CPUINT_NLEVELPERIPHS 21
#define EPS32_CPUINT_LEVELSET 0x8fbe333f
#define ESP32S2_CPUINT_LEVELSET 0x8fbe333f
#define ESP32S2_CPUINT_EDGEPERIPH_0 10
#define ESP32S2_CPUINT_EDGEPERIPH_1 22
@ -425,10 +421,10 @@
#define ESP32S2_CPUINT_EDGEPERIPH_3 30
#define ESP32S2_CPUINT_NEDGEPERIPHS 4
#define EPS32_CPUINT_EDGESET 0x50400400
#define ESP32S2_CPUINT_EDGESET 0x50400400
#define ESP32S2_CPUINT_NNMIPERIPHS 1
#define EPS32_CPUINT_NMISET 0x00004000
#define ESP32S2_CPUINT_NMISET 0x00004000
#define ESP32S2_CPUINT_MAC 0
#define ESP32S2_CPUINT_TIMER0 6
@ -442,8 +438,8 @@
#define ESP32S2_NCPUINTS 32
#define ESP32S2_CPUINT_MAX (ESP32S2_NCPUINTS - 1)
#define ESP32_CPUINT_PERIPHSET 0xdffe773f
#define EPS32_CPUINT_INTERNALSET 0x200188c0
#define ESP32S2_CPUINT_PERIPHSET 0xdffe773f
#define ESP32S2_CPUINT_INTERNALSET 0x200188c0
/* Priority 1: 0-10, 12-13, 17-18 (15)
* Priority 2: 19-21 (3)

8
arch/xtensa/src/esp32s2/esp32s2_cpuint.c
View File

@ -188,7 +188,7 @@ static uint32_t g_intenable[1];
* devices.
*/
static uint32_t g_cpu0_freeints = ESP32_CPUINT_PERIPHSET &
static uint32_t g_cpu0_freeints = ESP32S2_CPUINT_PERIPHSET &
(~ESP32S2_WIRELESS_RESERVE_INT);
/* Bitsets for each interrupt priority 1-5 */
@ -419,7 +419,8 @@ int esp32s2_alloc_levelint(int priority)
* interrupt priority.
*/
intmask = g_priority[ESP32S2_PRIO_INDEX(priority)] & EPS32_CPUINT_LEVELSET;
intmask = g_priority[ESP32S2_PRIO_INDEX(priority)] &
ESP32S2_CPUINT_LEVELSET;
return esp32s2_alloc_cpuint(intmask);
}
@ -451,7 +452,8 @@ int esp32s2_alloc_edgeint(int priority)
* interrupt priority.
*/
intmask = g_priority[ESP32S2_PRIO_INDEX(priority)] & EPS32_CPUINT_EDGESET;
intmask = g_priority[ESP32S2_PRIO_INDEX(priority)] &
ESP32S2_CPUINT_EDGESET;
return esp32s2_alloc_cpuint(intmask);
}