Fix assembly errors
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1490 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
0fcb411368
commit
7d2247f00c
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@ -1,5 +1,5 @@
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/************************************************************************************
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* arch/sh/src/m16c/chip.h
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* arch/sh/src/m16c/m16c_head.S
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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@ -48,40 +48,6 @@
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* Macro Definitions
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************************************************************************************/
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/* Zero a block of memory */
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.macro m16c_bzero, start, end
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mov.b #0x00, R0L
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mov.w #(\start & 0x0ffff), A1
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mov.w #(\end & 0x0ffff), R3
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sub.w A1, R3
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sstr.b
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.endm
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/* Copy a block of memory */
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.macro m16c_memcpy, dest, src, end
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mov.w #(\dest & 0x0ffff),A0
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mov.b #(\dest >> 16), R1H
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mov.w #\src, A1
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mov.w #(\end & 0x0ffff), R3
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sub.w A1, R3
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smovf.b
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.endm
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/* Special page vectors. This macro puts the jump address of
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* functions defined as special page into the special page vector table.
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* See example calls below and see the M16C Software Manual or NC30
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* manual for more information on special page vectors.
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*/
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#if 0
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.macro m16c_special, num
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.org 0x0ffffe-(\num*2)
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.globl __SPECIAL_\num
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.word __SPECIAL_\num & 0x0ffff
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.endm
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#endif
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/************************************************************************************
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* Data
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************************************************************************************/
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@ -96,242 +62,72 @@
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* 0x00bff - (end+1)
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*/
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.data
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#if 0
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.globl _g_istackbase
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.type _g_istackbase, object
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_g_istackbase:
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.word _enbss
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.size _g_istackbase, .-_g_istackbase
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.section .rodata
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.type _g_snbss, object
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_g_snbss:
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.word _g_snbss
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.size _g_snbss, .-_g_snbss
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.globl _g_stackbase
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.type _g_stackbase, object
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_g_stackbase:
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.word _enbss+CONFIG_ARCH_INTERRUPTSTACK
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.size _g_heapbase, .-_g_heapbase
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.size _g_istackbase, .-_g_istackbase
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.type _g_enbss, object
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_g_enbss:
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.word _g_enbss
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.size _g_enbss, .-_g_enbss
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.type _g_sndata, object
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_g_sndata:
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.word _g_sndata
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.size _g_sndata, .-_g_sndata
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.type _g_endata, object
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_g_endata:
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.word _g_endata
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.size _g_endata, .-_g_endata
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.type _g_enronly, object
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_g_enronly:
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.long _g_enronly
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.size _g_enronly, .-_g_efronly
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#ifdef CONFIG_M16C_HAVEFARRAM
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.type _g_sfbss, object
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_g_sfbss:
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.long _g_sfbss
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.size _g_sfbss, .-_g_sfbss
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.type _g_efbss, object
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_g_efbss:
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.long _g_efbss
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.size _g_efbss, .-_g_efbss
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.type _g_sfdata, object
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_g_sfdata:
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.long _g_sfdata
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.size _g_sfdata, .-_g_sfdata
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.type _g_efdata, object
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_g_efdata:
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.long _g_efdata
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.size _g_efdata, .-_g_efdata
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.type _g_efronly, object
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_g_efronly:
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.long _g_efronly
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.size _g_efronly, .-_g_efronly
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#endif
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.globl _g_heapbase
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.type _g_svarvect, object
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_g_svarvect:
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.long _svarvect
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.size _g_svarvect, .-_g_svarvect
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.type _g_heapbase, object
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_g_heapbase:
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.word _enbss+CONFIG_ARCH_INTERRUPTSTACK+CONFIG_IDLETHREAD_STACKSIZE
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.long _enbss+CONFIG_ARCH_INTERRUPTSTACK+CONFIG_IDLETHREAD_STACKSIZE
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.size _g_heapbase, .-_g_heapbase
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/************************************************************************************
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* Interrupt Vectors
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************************************************************************************/
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/* Variable vector section */
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.section varvects /* Variable vector table */
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.globl _m16c_unexpected_isr
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.globl _m16c_brk_isr
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.long _m16c_brk_isr /* ffd00: BRK instruction */
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.long 0xffffffff /* ffd04 */
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.long 0xffffffff /* ffd08 */
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.long 0xffffffff /* ffd0c */
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.globl _m16c_int3_isr
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.long _m16c_int3_isr /* ffd10: INT3 */
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#ifdef CONFIG_M16C_SWINTS
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.globl _m16c_swint5_isr
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.long _m16c_swint5_isr /* ffd14: S/W interrupt 5 */
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.globl _m16c_swint6_isr
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.long _m16c_swint6_isr /* ffd18: S/W interrupt 6 */
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.globl _m16c_swint7_isr
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.long _m16c_swint7_isr /* ffd1c: S/W interrupt 7 */
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#else
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.long _m16c_unexpected_isr /* ffd14: Reserved */
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.long _m16c_unexpected_isr /* ffd18: Reserved */
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.long _m16c_unexpected_isr /* ffd1c: Reserved */
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#endif
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.globl _m16c_int5_isr
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.long _m16c_int5_isr /* ffd20: INT5 */
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.globl _m16c_int4_isr
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.long _m16c_int4_isr /* ffd24: INT4 */
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.globl _m16c_uart2bcd_isr
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.long _m16c_uart2bcd_isr /* ffd28: UART2 bus collision detection */
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.globl _m16c_dma0_isr
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.long _m16c_dma0_isr /* ffd2c: DMA0 */
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.globl _m16c_dma1_isr
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.long _m16c_dma1_isr /* ffd30: DMA1 */
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.globl _m16c_keyinp_isr
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.long _m16c_keyinp_isr /* ffd34: Key input interrupt */
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.globl _m16c_adc_isr
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.long _m16c_adc_isr /* ffd38: A-D */
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.globl _m16c_uart2xmitnack2_isr
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.long _m16c_uart2xmitnack2_isr /* ffd3c UART2 transmit/NACK2 */
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.globl _m16c_uart2rcvack2_isr
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.long _m16c_uart2rcvack2_isr /* ffd40: UART2 receive/ACK2 */
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.globl _m16c_uart0xmit_isr
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.long _m16c_uart0xmit_isr /* ffd44: UART0 transmit */
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.globl _m16c_uart0rcv_isr
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.long _m16c_uart0rcv_isr /* ffd48: UART0 receive */
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.globl _m16c_uart1xmit_isr
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.long _m16c_uart1xmit_isr /* ffd4c: UART1 transmit */
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.globl _m16c_uart1rcv_isr
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.long _m16c_uart1rcv_isr /* ffd50: UART1 receive */
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.globl _m16c_tmra0_isr
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.long _m16c_tmra0_isr /* ffd54: Timer A0 */
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.globl _m16c_tmra1_isr
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.long _m16c_tmra1_isr /* ffd58: Timer A1 */
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.globl _m16c_tmra2_isr
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.long _m16c_tmra2_isr /* ffd5c: Timer A2 */
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.globl _m16c_tmra3_isr
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.long _m16c_tmra3_isr /* ffd60: Timer A3 */
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.globl _m16c_tmra4_isr
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.long _m16c_tmra4_isr /* ffd64: Timer A4 */
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.globl _m16c_tmrb0_isr
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.long _m16c_tmrb0_isr /* ffd68: Timer B0 */
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.globl _m16c_tmrb1_isr
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.long _m16c_tmrb1_isr /* ffd6c: Timer B1 */
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.globl _m16c_tmrb2_isr
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.long _m16c_tmrb2_isr /* ffd70: Timer B2 */
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.globl _m16c_int0_isr
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.long _m16c_int0_isr /* ffd74: INT0 */
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.globl _m16c_int1_isr
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.long _m16c_int1_isr /* ffd78: INT1 */
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#ifdef CONFIG_M16C_SWINTS
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.globl _m16c_swint31_isr
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.long _m16c_swint31_isr /* ffd7c: S/W interrupt 31 */
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.globl _m16c_swint32_isr
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.long _m16c_swint32_isr /* ffd80: S/W interrupt 32 */
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.globl _m16c_swint33_isr
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.long _m16c_swint33_isr /* ffd84: S/W interrupt 33 */
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.globl _m16c_swint34_isr
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.long _m16c_swint34_isr /* ffd88: S/W interrupt 34 */
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.globl _m16c_swint35_isr
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.long _m16c_swint35_isr /* ffd8c: S/W interrupt 35 */
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.globl _m16c_swint36_isr
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.long _m16c_swint36_isr /* ffd90: S/W interrupt 36 */
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.globl _m16c_swint37_isr
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.long _m16c_swint37_isr /* ffd94: S/W interrupt 37 */
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.globl _m16c_swint38_isr
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.long _m16c_swint38_isr /* ffd98: S/W interrupt 38 */
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.globl _m16c_swint39_isr
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.long _m16c_swint39_isr /* ffd9c: S/W interrupt 39 */
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.globl _m16c_swint40_isr
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.long _m16c_swint40_isr /* ffda0: S/W interrupt 40 */
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.globl _m16c_swint41_isr
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.long _m16c_swint41_isr /* ffda4: S/W interrupt 41 */
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.globl _m16c_swint42_isr
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.long _m16c_swint42_isr /* ffda8: S/W interrupt 42 */
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.globl _m16c_swint43_isr
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.long _m16c_swint43_isr /* ffdac: S/W interrupt 43 */
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.globl _m16c_swint44_isr
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.long _m16c_swint44_isr /* ffdb0: S/W interrupt 44 */
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.globl _m16c_swint45_isr
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.long _m16c_swint45_isr /* ffdb4: S/W interrupt 45 */
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.globl _m16c_swint46_isr
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.long _m16c_swint46_isr /* ffdb8: S/W interrupt 46 */
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.globl _m16c_swint47_isr
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.long _m16c_swint47_isr /* ffdbc: S/W interrupt 47 */
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.globl _m16c_swint48_isr
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.long _m16c_swint48_isr /* ffdc0: S/W interrupt 48 */
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.globl _m16c_swint49_isr
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.long _m16c_swint49_isr /* ffdc4: S/W interrupt 49 */
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.globl _m16c_swint50_isr
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.long _m16c_swint50_isr /* ffdc8: S/W interrupt 50 */
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.globl _m16c_swint51_isr
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.long _m16c_swint51_isr /* ffdcc: S/W interrupt 51 */
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.globl _m16c_swint52_isr
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.long _m16c_swint52_isr /* ffdd0: S/W interrupt 52 */
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.globl _m16c_swint53_isr
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.long _m16c_swint53_isr /* ffdd4: S/W interrupt 53 */
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.globl _m16c_swint54_isr
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.long _m16c_swint54_isr /* ffdd8: S/W interrupt 54 */
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.globl _m16c_swint55_isr
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.long _m16c_swint55_isr /* ffddc: S/W interrupt 55 */
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.globl _m16c_swint56_isr
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.long _m16c_swint56_isr /* ffde0: S/W interrupt 56 */
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.globl _m16c_swint57_isr
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.long _m16c_swint57_isr /* ffde4: S/W interrupt 57 */
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.globl _m16c_swint58_isr
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.long _m16c_swint58_isr /* ffde8: S/W interrupt 58 */
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.globl _m16c_swint59_isr
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.long _m16c_swint59_isr /* ffdec: S/W interrupt 59 */
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.globl _m16c_swint60_isr
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.long _m16c_swint60_isr /* ffdf0: S/W interrupt 60 */
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.globl _m16c_swint61_isr
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.long _m16c_swint61_isr /* ffdf4: S/W interrupt 61 */
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.globl _m16c_swint62_isr
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.long _m16c_swint62_isr /* ffdf8: S/W interrupt 62 */
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.globl _m16c_swint63_isr
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.long _m16c_swint63_isr /* ffdfc: S/W interrupt 63 */
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#else
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.long _m16c_unexpected_isr /* ffd7c: Reserved */
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.long _m16c_unexpected_isr /* ffd80: Not supported */
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.long _m16c_unexpected_isr /* ffd84: Not supported */
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.long _m16c_unexpected_isr /* ffd88: Not supported */
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.long _m16c_unexpected_isr /* ffd8c: Not supported */
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.long _m16c_unexpected_isr /* ffd90: Not supported */
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.long _m16c_unexpected_isr /* ffd94: Not supported */
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.long _m16c_unexpected_isr /* ffd98: Not supported */
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.long _m16c_unexpected_isr /* ffd9c: Not supported */
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.long _m16c_unexpected_isr /* ffda0: Not supported */
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.long _m16c_unexpected_isr /* ffda4: Not supported1 */
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.long _m16c_unexpected_isr /* ffda8: Not supported */
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.long _m16c_unexpected_isr /* ffdac: Not supported */
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.long _m16c_unexpected_isr /* ffdb0: Not supported */
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.long _m16c_unexpected_isr /* ffdb4: Not supported */
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.long _m16c_unexpected_isr /* ffdb8: Not supported */
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.long _m16c_unexpected_isr /* ffdbc: Not supported */
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.long _m16c_unexpected_isr /* ffdc0: Not supported */
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.long _m16c_unexpected_isr /* ffdc4: Not supported */
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.long _m16c_unexpected_isr /* ffdc8: Not supported */
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.long _m16c_unexpected_isr /* ffdcc: Not supported */
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.long _m16c_unexpected_isr /* ffdd0: Not supported */
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.long _m16c_unexpected_isr /* ffdd4: Not supported */
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.long _m16c_unexpected_isr /* ffdd8: Not supported */
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.long _m16c_unexpected_isr /* ffddc: Not supported */
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.long _m16c_unexpected_isr /* ffde0: Not supported */
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.long _m16c_unexpected_isr /* ffde4: Not supported */
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.long _m16c_unexpected_isr /* ffde8: Not supported */
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.long _m16c_unexpected_isr /* ffdec: Not supported */
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.long _m16c_unexpected_isr /* ffdf0: Not supported */
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.long _m16c_unexpected_isr /* ffdf4: Not supported */
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.long _m16c_unexpected_isr /* ffdf8: Not supported */
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.long _m16c_unexpected_isr /* ffdfc: Not supported */
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#endif
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/* Fixed vector section
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*
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* The fixed vector table begins at address ffe00. The firt portion
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* of the fixed vector table is the special page table. This table
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* is not currently used.
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*/
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.section specpg /* Special page table */
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.section fixvects /* Fixed vector table */
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.globl _m16c_undefinst_irq
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.long _m16c_undefinst_irq /* fffdc: Undefined instruction */
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.globl _m16c_overflow_irq
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.long _m16c_overflow_irq /* fffe0: Overflow */
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.globl _m16c_brkinst_irq
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.long _m16c_brkinst_irq /* fffe4: BRK instruction */
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.globl _m16c_addrmatch_irq
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.long _m16c_addrmatch_irq /* fffe8: Address match */
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#ifdef CONFIG_M16C_DEBUGGER
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.globl _m16c_sstep_irq
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.long _m16c_sstep_irq /* fffec: Single step */
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#else
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.long _m16c_unexpected_isr /* fffec: Not supported */
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#endif
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.globl _m16c_wdog_irq
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.long _m16c_wdog_irq /* ffff0: Watchdog timer */
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#ifdef CONFIG_M16C_DEBUGGER
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.globl _m16c_dbc_irq
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.long _m16c_dbc_irq /* ffff4: DBC */
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#else
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.long _m16c_unexpected_isr /* ffff4: Not supported */
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#endif
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.globl _m16c_nmi_irq
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.long _m16c_nmi_irq /* ffff8: NMI */
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.long __start /* ffffc: Reset */
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/************************************************************************************
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* Code
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************************************************************************************/
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/************************************************************************************
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* Name: _start
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*
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@ -371,22 +167,40 @@ __start:
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mov.b #0xc0, M16C_IFSR /* Set b7 & b6 if application will use INT4 & INT5 */
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ldc #M16C_IRAM_BASE, sb /* Set sb register (to what?) */
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.globl _svarvect
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ldc #(_svarvect >> 8), intbh
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ldc #_svarvect, intbl
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/* Set up INTB to point to location of variable vector table */
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/* Clear .bss sections */
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mov.w _g_svarvect, r0 /* R0 = lower 16-bits */
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mov.w _g_svarvect+2, r1 /* R1 = upper 4-bits */
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ldc r1, intbh
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ldc r0, intbl
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/* Clear near .bss sections */
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mov.b #0x00, r0l /* r0l: 0 */
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mov.w _g_snbss, a1 /* a1: start of near .bss */
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mov.w _g_enbss, r3 /* r3: end of near .bss */
|
||||
sub.w a1, r3 /* r3: size of near .bss */
|
||||
sstr.b /* Clear near .bss */
|
||||
|
||||
/* Clear far .bss sections */
|
||||
|
||||
m16c_bzero _snbss, _enbss
|
||||
#ifdef CONFIG_M16C_HAVEFARRAM
|
||||
m16c_bzero _sfbss, _efbss
|
||||
# warning "Far RAM support not implemented"
|
||||
#endif
|
||||
|
||||
/* Initialize .data sections */
|
||||
/* Initialize near .data sections (.rodata is not moved) */
|
||||
|
||||
mov.w _g_enronly, a0 /* a0: Low 16 bits of source */
|
||||
mov.b _g_enronly+2, r1h /* r1h: 4 order bits of source */
|
||||
mov.w _g_sndata, a1 /* a1: start of near .data */
|
||||
mov.w _g_endata, r3 /* r3: end of near .data */
|
||||
sub.w a1, r3 /* r3: size of near .data */
|
||||
smovf.b /* Copy source to near .data */
|
||||
|
||||
/* Initialize far .data sections (.rodata is not moved) */
|
||||
|
||||
m16c_memcpy _sndata, _enronly, _endata
|
||||
#ifdef CONFIG_M16C_HAVEFARRAM
|
||||
m16c_memcpy _sfdata, _efronly, _efdata
|
||||
# warning "Far RAM support not implemented"
|
||||
#endif
|
||||
|
||||
/* Pass control to NuttX */
|
||||
|
|
|
|||
Loading…
Reference in New Issue