From 75a97657be7d708131e808cd6a53bb4057f5f6e5 Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Tue, 19 Mar 2019 11:22:44 -0600 Subject: [PATCH] arch/arm/src/armv7-a/sctlr.h: Add SCR bit definitions. --- arch/arm/src/armv7-a/sctlr.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/armv7-a/sctlr.h b/arch/arm/src/armv7-a/sctlr.h index 10511156a4..6d3fce9526 100644 --- a/arch/arm/src/armv7-a/sctlr.h +++ b/arch/arm/src/armv7-a/sctlr.h @@ -167,7 +167,19 @@ /* TODO: To be provided */ /* Secure Configuration Register (SCR) */ -/* TODO: To be provided */ + +#define SCR_NS (1 << 0) /* Bit 0: Non-secure */ +#define SCR_IRQ (1 << 1) /* Bit 1: IRQs taken in Monitor mode */ +#define SCR_FIQ (1 << 2) /* Bit 2: FIQs taken in Monitor mode */ +#define SCR_EA (1 << 3) /* Bit 3: External aborts taken in Monitor mode */ +#define SCR_FW (1 << 4) /* Bit 4: F bit writable */ +#define SCR_AW (1 << 5) /* Bit 5: A bit writable */ +#define SCR_NET (1 << 6) /* Bit 6: Not Early Termination */ +#define SCR_SCD (1 << 7) /* Bit 7: Secure Monitor Call disable */ +#define SCR_HCE (1 << 8) /* Bit 8: Hyp Call enable */ +#define SCR_SIF (1 << 9) /* Bit 9: Secure state instruction fetches from + * Non-secure memory are not permitted */ + /* Bits 10-31: Reserved */ /* Secure Debug Enable Register (SDER) */ /* TODO: To be provided */