Handle LM4F GPIO -- fewer ports
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5695 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
parent
052b9dc37d
commit
735ef1ad7a
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@ -42,10 +42,32 @@
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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#include <arch/lm/chip.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Mark GPIO interrupts as disabled for non-existent GPIO ports. */
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#if LM_NPORTS < 1 && !defined(CONFIG_LM_DISABLE_GPIOA_IRQS)
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# define CONFIG_LM_DISABLE_GPIOA_IRQS
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#elif LM_NPORTS < 2 && !defined(CONFIG_LM_DISABLE_GPIOB_IRQS)
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# define CONFIG_LM_DISABLE_GPIOB_IRQS
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#elif LM_NPORTS < 3 && !defined(CONFIG_LM_DISABLE_GPIOC_IRQS)
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# define CONFIG_LM_DISABLE_GPIOC_IRQS
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#elif LM_NPORTS < 4 && !defined(CONFIG_LM_DISABLE_GPIOD_IRQS)
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# define CONFIG_LM_DISABLE_GPIOD_IRQS
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#elif LM_NPORTS < 5 && !defined(CONFIG_LM_DISABLE_GPIOE_IRQS)
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# define CONFIG_LM_DISABLE_GPIOE_IRQS
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#elif LM_NPORTS < 6 && !defined(CONFIG_LM_DISABLE_GPIOF_IRQS)
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# define CONFIG_LM_DISABLE_GPIOF_IRQS
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#elif LM_NPORTS < 7 && !defined(CONFIG_LM_DISABLE_GPIOG_IRQS)
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# define CONFIG_LM_DISABLE_GPIOG_IRQS
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#elif LM_NPORTS < 8 && !defined(CONFIG_LM_DISABLE_GPIOH_IRQS)
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# define CONFIG_LM_DISABLE_GPIOH_IRQS
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#elif LM_NPORTS < 9 && !defined(CONFIG_LM_DISABLE_GPIOJ_IRQS)
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# define CONFIG_LM_DISABLE_GPIOJ_IRQS
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#endif
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/* Processor Exceptions (vectors 0-15) */
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@ -60,23 +60,67 @@
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/* NOTE: this is duplicated in lm_gpio.c */
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#ifdef LM_GPIOH_BASE
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static const uint32_t g_gpiobase[8] =
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static const uintptr_t g_gpiobase[LM_NPORTS] =
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{
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LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE,
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LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE, LM_GPIOH_BASE,
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};
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static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
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#else
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static const uint32_t g_gpiobase[8] =
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{
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LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE,
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LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE, 0,
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};
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static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' };
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#if LM_NPORTS > 0
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LM_GPIOA_BASE
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#endif
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#if LM_NPORTS > 1
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, LM_GPIOB_BASE
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#endif
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#if LM_NPORTS > 2
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, LM_GPIOC_BASE
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#endif
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#if LM_NPORTS > 3
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, LM_GPIOD_BASE
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#endif
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#if LM_NPORTS > 4
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, LM_GPIOE_BASE
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#endif
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#if LM_NPORTS > 5
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, LM_GPIOF_BASE
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#endif
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#if LM_NPORTS > 6
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, LM_GPIOG_BASE
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#endif
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#if LM_NPORTS > 7
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, LM_GPIOH_BASE
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#endif
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#if LM_NPORTS > 8
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, LM_GPIOJ_BASE
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#endif
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};
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static const char g_portchar[LM_NPORTS] =
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{
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#if LM_NPORTS > 0
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'A'
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#endif
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#if LM_NPORTS > 1
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, 'B'
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#endif
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#if LM_NPORTS > 2
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, 'C'
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#endif
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#if LM_NPORTS > 3
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, 'D'
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#endif
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#if LM_NPORTS > 4
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, 'E'
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#endif
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#if LM_NPORTS > 5
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, 'F'
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#endif
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#if LM_NPORTS > 6
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, 'G'
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#endif
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#if LM_NPORTS > 7
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, 'H'
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#endif
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#if LM_NPORTS > 8
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, 'J'
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#endif
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};
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/****************************************************************************
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* Private Functions
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@ -91,9 +135,9 @@ static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' };
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*
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****************************************************************************/
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static inline uint32_t lm_gpiobaseaddress(int port)
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static inline uintptr_t lm_gpiobaseaddress(int port)
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{
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return g_gpiobase[port & 7];
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return port < LM_NPORTS ? g_gpiobase[port] : 0;
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}
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/****************************************************************************
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@ -107,7 +151,7 @@ static inline uint32_t lm_gpiobaseaddress(int port)
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static inline uint8_t lm_gpioport(int port)
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{
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return g_portchar[port & 7];
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return port < LM_NPORTS ? g_portchar[port] : '?';
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}
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/****************************************************************************
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@ -126,7 +170,7 @@ int lm_dumpgpio(uint32_t pinset, const char *msg)
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{
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irqstate_t flags;
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unsigned int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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uint32_t base;
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uintptr_t base;
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uint32_t rcgc2;
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bool enabled;
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@ -140,23 +140,36 @@ static const struct gpio_func_s g_funcbits[] =
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{GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */
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};
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static const uint32_t g_gpiobase[LM_NPORTS] =
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/* NOTE: this is duplicated in lm_dumpgpio.c */
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static const uintptr_t g_gpiobase[LM_NPORTS] =
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{
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/* All support Stellaris parts have at least 7 ports, GPIOA-G */
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LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE,
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LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE,
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/* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/
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#if LM_NPORTS > 7
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LM_GPIOH_BASE,
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#if LM_NPORTS > 0
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LM_GPIOA_BASE
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#endif
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#if LM_NPORTS > 1
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, LM_GPIOB_BASE
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#endif
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#if LM_NPORTS > 2
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, LM_GPIOC_BASE
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#endif
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#if LM_NPORTS > 3
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, LM_GPIOD_BASE
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#endif
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#if LM_NPORTS > 4
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, LM_GPIOE_BASE
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#endif
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#if LM_NPORTS > 5
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, LM_GPIOF_BASE
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#endif
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#if LM_NPORTS > 6
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, LM_GPIOG_BASE
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#endif
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#if LM_NPORTS > 7
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, LM_GPIOH_BASE
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#endif
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/* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/
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#if LM_NPORTS > 8
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LM_GPIOJ_BASE,
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, LM_GPIOJ_BASE
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#endif
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};
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@ -177,13 +190,14 @@ static const uint32_t g_gpiobase[LM_NPORTS] =
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*
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****************************************************************************/
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static uint32_t lm_gpiobaseaddress(unsigned int port)
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static uintptr_t lm_gpiobaseaddress(unsigned int port)
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{
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uint32_t gpiobase = 0;
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uintptr_t gpiobase = 0;
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if (port < LM_NPORTS)
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{
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gpiobase = g_gpiobase[port];
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}
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return gpiobase;
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}
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@ -707,8 +721,8 @@ int lm_configgpio(uint32_t cfgset)
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unsigned int func;
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unsigned int port;
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unsigned int pinno;
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uintptr_t base;
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uint32_t pin;
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uint32_t base;
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uint32_t regval;
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/* Decode the basics */
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@ -787,7 +801,7 @@ void lm_gpiowrite(uint32_t pinset, bool value)
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{
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unsigned int port;
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unsigned int pinno;
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uint32_t base;
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uintptr_t base;
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/* Decode the basics */
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@ -825,7 +839,7 @@ bool lm_gpioread(uint32_t pinset, bool value)
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{
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unsigned int port;
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unsigned int pinno;
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uint32_t base;
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uintptr_t base;
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/* Decode the basics */
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@ -70,45 +70,40 @@ static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS];
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* must carefully match the IRQ numbers assigned in arch/arm/include/lm3s/irq.h
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*/
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static const uint32_t g_gpiobase[] =
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static const uintptr_t g_gpiobase[] =
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{
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#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
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LM_GPIOA_BASE,
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LM_GPIOA_BASE
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#else
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0
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#endif
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#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
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LM_GPIOB_BASE,
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, LM_GPIOB_BASE
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#endif
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#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
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LM_GPIOC_BASE,
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, LM_GPIOC_BASE
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#endif
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#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
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LM_GPIOD_BASE,
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, LM_GPIOD_BASE
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#endif
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#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
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LM_GPIOE_BASE,
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, LM_GPIOE_BASE
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#endif
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#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
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LM_GPIOF_BASE,
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, LM_GPIOF_BASE
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#endif
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#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
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LM_GPIOG_BASE,
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, LM_GPIOG_BASE
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#endif
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/* NOTE: Not all Stellaris architectures support GPIOs above GPIOG. If the
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* chip does not support these higher ports, then they must be disabled in
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* the configuration. Otherwise, the following will likely cause compilation
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* errors!
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*/
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#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
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LM_GPIOH_BASE,
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, LM_GPIOH_BASE
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#endif
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#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
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LM_GPIOJ_BASE,
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, LM_GPIOJ_BASE
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#endif
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};
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#define GPIO_NADDRS (sizeof(g_gpiobase)/sizeof(uint32_t))
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#define GPIO_NADDRS (sizeof(g_gpiobase)/sizeof(uintptr_t))
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/****************************************************************************
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* Public Data
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@ -131,13 +126,14 @@ static const uint32_t g_gpiobase[] =
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*
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****************************************************************************/
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static uint32_t lm_gpiobaseaddress(unsigned int gpioirq)
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static uintptr_t lm_gpiobaseaddress(unsigned int gpioirq)
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{
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unsigned int ndx = gpioirq >> 3;
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if (ndx < GPIO_NADDRS)
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{
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return g_gpiobase[ndx];
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}
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return 0;
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}
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@ -366,7 +362,7 @@ void gpio_irqenable(int irq)
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{
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irqstate_t flags;
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int gpioirq = irq - NR_IRQS;
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uint32_t base;
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uintptr_t base;
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uint32_t regval;
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int pin;
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@ -405,7 +401,7 @@ void gpio_irqdisable(int irq)
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{
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irqstate_t flags;
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int gpioirq = irq - NR_IRQS;
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uint32_t base;
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uintptr_t base;
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uint32_t regval;
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int pin;
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