stm32h7:i2c driver fixed iterrupt storm
Driver was getting into a state that it would keep generating interrups and not service them.
This commit is contained in:
David Sidrane
Xiang Xiao
parent
e67f72b02d
commit
719246eddc
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@ -20,7 +20,6 @@
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* Copyright (c) 2016 Doug Vetter. All rights reserved.
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* Author: Doug Vetter <oss@aileronlabs.com>
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@ -115,7 +114,7 @@
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*
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* - Private: Private data of an I2C Hardware
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*
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* High Level Functional Desecription
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* High Level Functional Description
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*
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* This driver works with I2C "messages" (struct i2c_msg_s), which carry a buffer
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* intended to transfer data to, or store data read from, the I2C bus.
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@ -140,7 +139,7 @@
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* Interrupt mode relies on the following interrupt events:
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*
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* TXIS - Transmit interrupt
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* (data transmitted to bus and acknowedged)
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* (data transmitted to bus and acknowledged)
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* NACKF - Not Acknowledge Received
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* (data transmitted to bus and NOT acknowledged)
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* RXNE - Receive interrupt
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@ -284,9 +283,15 @@
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#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
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#define I2C_CR1_TXRX (I2C_CR1_RXIE | I2C_CR1_TXIE)
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#define I2C_CR1_TXRX (I2C_CR1_RXIE | I2C_CR1_TXIE)
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#define I2C_CR1_ALLINTS (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE)
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/* Unused bit in I2c_ISR used to communicate a bad state has occurred in
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* the isr processing
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*/
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#define I2C_INT_BAD_STATE 0x8000000
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/* I2C event tracing
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*
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* To enable tracing statements which show the details of the state machine
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@ -358,7 +363,7 @@ struct stm32_trace_s
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uint32_t count; /* Interrupt count when status change */
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enum stm32_intstate_e event; /* Last event that occurred with this status */
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uint32_t parm; /* Parameter associated with the event */
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uint32_t time; /* First of event or first status */
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clock_t time; /* First of event or first status */
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};
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/* I2C Device hardware configuration */
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@ -403,7 +408,7 @@ struct stm32_i2c_priv_s
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#ifdef CONFIG_I2C_TRACE
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int tndx; /* Trace array index */
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uint32_t start_time; /* Time when the trace was started */
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clock_t start_time; /* Time when the trace was started */
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/* The actual trace data */
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@ -833,9 +838,9 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
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#else
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static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
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{
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uint32_t timeout;
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uint32_t start;
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uint32_t elapsed;
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clock_t timeout;
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clock_t start;
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clock_t elapsed;
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int ret;
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/* Get the timeout value */
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@ -871,8 +876,8 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
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while (priv->intstate != INTSTATE_DONE && elapsed < timeout);
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i2cinfo("intstate: %d elapsed: %d threshold: %d status: 0x%08x\n",
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priv->intstate, elapsed, timeout, priv->status);
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i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: 0x%08x\n",
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priv->intstate, (long)elapsed, (long)timeout, priv->status);
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/* Set the interrupt state back to IDLE */
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@ -973,9 +978,9 @@ stm32_i2c_disable_reload(FAR struct stm32_i2c_priv_s *priv)
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static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
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{
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uint32_t start;
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uint32_t elapsed;
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uint32_t timeout;
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clock_t start;
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clock_t elapsed;
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clock_t timeout;
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uint32_t cr;
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uint32_t sr;
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@ -1055,7 +1060,8 @@ static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev)
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*/
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nxsem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0);
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nxsem_set_protocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE);
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nxsem_set_protocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr,
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SEM_PRIO_NONE);
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#endif
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}
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@ -1177,7 +1183,7 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
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int i;
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syslog(LOG_DEBUG, "Elapsed time: %d\n",
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clock_systime_ticks() - priv->start_time);
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(int)(clock_systime_ticks() - priv->start_time));
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for (i = 0; i < priv->tndx; i++)
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{
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@ -1185,7 +1191,7 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
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syslog(LOG_DEBUG,
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"%2d. STATUS: %08x COUNT: %3d EVENT: %2d PARM: %08x TIME: %d\n",
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i + 1, trace->status, trace->count, trace->event, trace->parm,
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trace->time - priv->start_time);
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(int)(trace->time - priv->start_time));
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}
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}
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#endif /* CONFIG_I2C_TRACE */
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@ -1243,24 +1249,21 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
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static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequency)
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{
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uint32_t pe;
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uint8_t presc;
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uint8_t scl_delay;
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uint8_t sda_delay;
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uint8_t scl_h_period;
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uint8_t scl_l_period;
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/* I2C peripheral must be disabled to update clocking configuration.
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* This will SW reset the device.
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*/
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stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
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if (frequency != priv->frequency)
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{
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/* I2C peripheral must be disabled to update clocking configuration */
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pe = (stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE);
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if (pe)
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{
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stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
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}
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/* The Sppeed and timing calculation are based on the following
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/* The Speed and timing calculation are based on the following
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* fI2CCLK = HSI and is 16Mhz
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* Analog filter is on,
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* Digital filter off
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@ -1309,14 +1312,12 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
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(scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
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stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr);
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if (pe)
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{
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stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
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}
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priv->frequency = frequency;
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}
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/* Enable I2C peripheral */
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stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
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}
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/************************************************************************************
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@ -1533,9 +1534,9 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
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i2cinfo("ENTER: status = 0x%08x\n", status);
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/* Update private version of the state */
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/* Update private version of the state assuming a good state */
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priv->status = status;
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priv->status = status & ~I2C_INT_BAD_STATE;
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/* If this is a new transmission set up the trace table accordingly */
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@ -1611,7 +1612,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
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* interrupt will only fire when the I2C_CR1->TXIE bit is 1.
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*
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* This indicates the transmit data register I2C_TXDR has been emptied
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* following the successful transmission of a byte and slave acknowledgement.
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* following the successful transmission of a byte and slave acknowledgment.
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* In this state the I2C_TXDR register is ready to accept another byte for
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* transmission. The TXIS bit will be cleared automatically when the next
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* byte is written to I2C_TXDR.
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@ -1701,6 +1702,10 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
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i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, status 0x%08x\n",
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priv->dcnt, status);
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stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0);
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/* Indicate the bad state, so that on termination HW will be reset */
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priv->status |= I2C_INT_BAD_STATE;
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}
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i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08x\n",
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@ -1789,6 +1794,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
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/* Set signals that will terminate ISR and wake waiting thread */
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priv->status |= I2C_INT_BAD_STATE;
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priv->dcnt = -1;
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priv->msgc = 0;
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}
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@ -2034,7 +2040,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
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*
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* We get to this branch only if we can't handle the current state.
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*
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* This should not happen in interrupt based operation.
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* This can happen in interrupt based operation on ARLO & BUSY.
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*
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* This will happen during polled operation when the device is not
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* in one of the supported states when polled.
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@ -2053,6 +2059,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
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/* set condition to terminate ISR and wake waiting thread */
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priv->status |= I2C_INT_BAD_STATE;
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priv->dcnt = -1;
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priv->msgc = 0;
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stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0);
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@ -2084,8 +2091,6 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
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priv->intstate = INTSTATE_DONE;
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#else
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status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
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/* Update private state to capture NACK which is used in combination
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* with the astart flag to report the type of NACK received (address
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* vs data) to the upper layers once we exit the ISR.
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@ -2094,12 +2099,25 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
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* flag will naturally be cleared by that process.
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*/
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priv->status = status;
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status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
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/* Clear all interrupts */
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stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
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/* Was a bad state detected in the processing? */
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if (priv->status & I2C_INT_BAD_STATE)
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{
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/* SW reset device */
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stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
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}
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/* Update private status from above sans I2C_INT_BAD_STATE */
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priv->status = status;
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/* If a thread is waiting then inform it transfer is complete */
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if (priv->intstate == INTSTATE_WAITING)
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@ -2184,10 +2202,6 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
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priv->frequency = 0;
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stm32_i2c_setclock(priv, 100000);
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/* Enable I2C peripheral */
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stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
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return OK;
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}
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@ -2268,7 +2282,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev,
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stm32_i2c_tracereset(priv);
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/* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) */
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/* Set I2C clock frequency toggles I2C_CR1_PE performing a SW reset! */
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stm32_i2c_setclock(priv, msgs->frequency);
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@ -2434,8 +2448,8 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev,
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* wraps up the transfer with a STOP condition.
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*/
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uint32_t start = clock_systime_ticks();
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uint32_t timeout = USEC2TICK(USEC_PER_SEC / priv->frequency) + 1;
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clock_t start = clock_systime_ticks();
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clock_t timeout = USEC2TICK(USEC_PER_SEC / priv->frequency) + 1;
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status = stm32_i2c_getstatus(priv);
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@ -2685,6 +2699,12 @@ static int stm32_i2c_pm_prepare(FAR struct pm_callback_s *cb, int domain,
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}
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break;
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default:
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/* Should not get here */
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break;
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}
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return OK;
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