From 70caa27c4cf5af0fbd043c4fa6c8e1935665d13d Mon Sep 17 00:00:00 2001
From: Nathan Hartman <59230071+hartmannathan@users.noreply.github.com>
Date: Fri, 11 Sep 2020 11:15:53 -0400
Subject: [PATCH] tiva: tiva_dumpgpio.c: Fix nxstyle warnings

arch/arm/src/tiva/common/tiva_dumpgpio.c:

    * Fix nxstyle warnings. No functional changes.
---
 arch/arm/src/tiva/common/tiva_dumpgpio.c | 27 ++++++++++++++++--------
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/arch/arm/src/tiva/common/tiva_dumpgpio.c b/arch/arm/src/tiva/common/tiva_dumpgpio.c
index fe9c9a2993..8e0b92bc81 100644
--- a/arch/arm/src/tiva/common/tiva_dumpgpio.c
+++ b/arch/arm/src/tiva/common/tiva_dumpgpio.c
@@ -183,15 +183,24 @@ int tiva_dumpgpio(uint32_t pinset, const char *msg)
   if (enabled)
     {
       gpioinfo("   AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n",
-               getreg32(base + TIVA_GPIO_AFSEL_OFFSET), getreg32(base + TIVA_GPIO_DEN_OFFSET),
-               getreg32(base + TIVA_GPIO_DIR_OFFSET), getreg32(base + TIVA_GPIO_DATA_OFFSET + 0x3fc));
-      gpioinfo("      IS:  %02x IBE: %02x IEV: %02x IM:  %02x RIS: %08x MIS: %08x\n",
-               getreg32(base + TIVA_GPIO_IEV_OFFSET), getreg32(base + TIVA_GPIO_IM_OFFSET),
-               getreg32(base + TIVA_GPIO_RIS_OFFSET), getreg32(base + TIVA_GPIO_MIS_OFFSET));
-      gpioinfo("     2MA:  %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n",
-               getreg32(base + TIVA_GPIO_DR2R_OFFSET), getreg32(base + TIVA_GPIO_DR4R_OFFSET),
-               getreg32(base + TIVA_GPIO_DR8R_OFFSET), getreg32(base + TIVA_GPIO_ODR_OFFSET),
-               getreg32(base + TIVA_GPIO_PUR_OFFSET), getreg32(base + TIVA_GPIO_PDR_OFFSET),
+               getreg32(base + TIVA_GPIO_AFSEL_OFFSET),
+               getreg32(base + TIVA_GPIO_DEN_OFFSET),
+               getreg32(base + TIVA_GPIO_DIR_OFFSET),
+               getreg32(base + TIVA_GPIO_DATA_OFFSET + 0x3fc));
+      gpioinfo("      IS:  %02x IBE: %02x IEV: %02x IM:  %02x "
+               "RIS: %08x MIS: %08x\n",
+               getreg32(base + TIVA_GPIO_IEV_OFFSET),
+               getreg32(base + TIVA_GPIO_IM_OFFSET),
+               getreg32(base + TIVA_GPIO_RIS_OFFSET),
+               getreg32(base + TIVA_GPIO_MIS_OFFSET));
+      gpioinfo("     2MA:  %02x 4MA: %02x 8MA: %02x ODR: %02x "
+               "PUR %02x PDR: %02x SLR: %02x\n",
+               getreg32(base + TIVA_GPIO_DR2R_OFFSET),
+               getreg32(base + TIVA_GPIO_DR4R_OFFSET),
+               getreg32(base + TIVA_GPIO_DR8R_OFFSET),
+               getreg32(base + TIVA_GPIO_ODR_OFFSET),
+               getreg32(base + TIVA_GPIO_PUR_OFFSET),
+               getreg32(base + TIVA_GPIO_PDR_OFFSET),
                getreg32(base + TIVA_GPIO_SLR_OFFSET));
     }