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STM32 SPI: The source clock for SPI 4,5, and 6 should be PCLK2, not PCLK1 (for F411, F427, and F429). Per David Sidrane.

This commit is contained in:
Gregory Nutt 2015-02-07 13:59:45 -06:00
parent 8f4bbdd057
commit 6f335dc6c6
2 changed files with 4 additions and 3 deletions
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6
arch/arm/src/stm32/stm32_spi.c
View File

@ -409,7 +409,7 @@ static struct stm32_spidev_s g_spi4dev =
{ {
.spidev = { &g_sp4iops }, .spidev = { &g_sp4iops },
.spibase = STM32_SPI4_BASE, .spibase = STM32_SPI4_BASE,
.spiclock = STM32_PCLK1_FREQUENCY, .spiclock = STM32_PCLK2_FREQUENCY,
#ifdef CONFIG_STM32_SPI_INTERRUPTS #ifdef CONFIG_STM32_SPI_INTERRUPTS
.spiirq = STM32_IRQ_SPI4, .spiirq = STM32_IRQ_SPI4,
#endif #endif
@ -448,7 +448,7 @@ static struct stm32_spidev_s g_spi5dev =
{ {
.spidev = { &g_sp5iops }, .spidev = { &g_sp5iops },
.spibase = STM32_SPI5_BASE, .spibase = STM32_SPI5_BASE,
.spiclock = STM32_PCLK1_FREQUENCY, .spiclock = STM32_PCLK2_FREQUENCY,
#ifdef CONFIG_STM32_SPI_INTERRUPTS #ifdef CONFIG_STM32_SPI_INTERRUPTS
.spiirq = STM32_IRQ_SPI5, .spiirq = STM32_IRQ_SPI5,
#endif #endif
@ -487,7 +487,7 @@ static struct stm32_spidev_s g_spi6dev =
{ {
.spidev = { &g_sp6iops }, .spidev = { &g_sp6iops },
.spibase = STM32_SPI6_BASE, .spibase = STM32_SPI6_BASE,
.spiclock = STM32_PCLK1_FREQUENCY, .spiclock = STM32_PCLK2_FREQUENCY,
#ifdef CONFIG_STM32_SPI_INTERRUPTS #ifdef CONFIG_STM32_SPI_INTERRUPTS
.spiirq = STM32_IRQ_SPI6, .spiirq = STM32_IRQ_SPI6,
#endif #endif

1
drivers/serial/lowconsole.c
View File

@ -115,6 +115,7 @@ static ssize_t lowconsole_write(struct file *filep, const char *buffer, size_t b
{ {
up_putc(*buffer++); up_putc(*buffer++);
} }
return ret; return ret;
} }