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esp32[s2|s3]: move rom segments mapping to espressif common folder 

Move and unify map_rom_segments function called when starting
Simple Boot and MCUboot compatible images.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
This commit is contained in:
Almir Okato 2024-06-10 16:52:28 +02:00 committed by Alan Carvalho de Assis
parent 6b79aea0cf
commit 6ec690cbfc
10 changed files with 78 additions and 279 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/xtensa/src/common/espressif/Make.defs
View File

@ -29,4 +29,10 @@ ifeq ($(CONFIG_ESP_MCPWM),y)
CHIP_CSRCS += esp_mcpwm.c
endif
ifeq ($(filter $(CONFIG_ESPRESSIF_SIMPLE_BOOT) \
$(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) \
$(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y),y)
CHIP_CSRCS += esp_loader.c
endif
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common$(DELIM)espressif$(DELIM)platform_include

85
arch/xtensa/src/esp32s2/loader.c → arch/xtensa/src/common/espressif/esp_loader.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/loader.c
* arch/xtensa/src/common/espressif/esp_loader.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -51,54 +51,48 @@
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
# define HDR_ATTR __attribute__((section(".entry_addr"))) \
__attribute__((used))
# define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */
# define CACHE_REG EXTMEM_ICACHE_CTRL1_REG
# define CACHE_MASK (EXTMEM_ICACHE_SHUT_IBUS_M | \
EXTMEM_ICACHE_SHUT_DBUS_M)
# define CHECKSUM_ALIGN 16
# define IS_PADD(addr) (addr == 0)
# define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH)
# define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH)
# define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH)
# define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH)
# define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr))
# define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr))
# ifdef SOC_RTC_FAST_MEM_SUPPORTED
# define IS_RTC_FAST_IRAM(addr) \
(addr >= SOC_RTC_IRAM_LOW && addr < SOC_RTC_IRAM_HIGH)
# define IS_RTC_FAST_DRAM(addr) \
(addr >= SOC_RTC_DRAM_LOW && addr < SOC_RTC_DRAM_HIGH)
# else
# define IS_RTC_FAST_IRAM(addr) 0
# define IS_RTC_FAST_DRAM(addr) 0
# endif
# ifdef SOC_RTC_SLOW_MEM_SUPPORTED
# define IS_RTC_SLOW_DRAM(addr) \
(addr >= SOC_RTC_DATA_LOW && addr < SOC_RTC_DATA_HIGH)
# else
# define IS_RTC_SLOW_DRAM(addr) 0
# endif
# define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \
&& !IS_IRAM(addr) && !IS_DRAM(addr) \
&& !IS_RTC_FAST_IRAM(addr) && !IS_RTC_FAST_DRAM(addr) \
&& !IS_RTC_SLOW_DRAM(addr) && !IS_PADD(addr))
# define IS_MAPPING(addr) IS_IROM(addr) || IS_DROM(addr)
#define HDR_ATTR __attribute__((section(".entry_addr"))) \
__attribute__((used))
#define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */
#define CACHE_REG EXTMEM_ICACHE_CTRL1_REG
#define CACHE_MASK (EXTMEM_ICACHE_SHUT_IBUS_M | \
EXTMEM_ICACHE_SHUT_DBUS_M)
#define CHECKSUM_ALIGN 16
#define IS_PADD(addr) (addr == 0)
#define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH)
#define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH)
#define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH)
#define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH)
#define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr))
#define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr))
#ifdef SOC_RTC_FAST_MEM_SUPPORTED
# define IS_RTC_FAST_IRAM(addr) \
(addr >= SOC_RTC_IRAM_LOW && addr < SOC_RTC_IRAM_HIGH)
# define IS_RTC_FAST_DRAM(addr) \
(addr >= SOC_RTC_DRAM_LOW && addr < SOC_RTC_DRAM_HIGH)
#else
# define IS_RTC_FAST_IRAM(addr) 0
# define IS_RTC_FAST_DRAM(addr) 0
#endif
#ifdef SOC_RTC_SLOW_MEM_SUPPORTED
# define IS_RTC_SLOW_DRAM(addr) \
(addr >= SOC_RTC_DATA_LOW && addr < SOC_RTC_DATA_HIGH)
#else
# define IS_RTC_SLOW_DRAM(addr) 0
#endif
#define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \
&& !IS_IRAM(addr) && !IS_DRAM(addr) \
&& !IS_RTC_FAST_IRAM(addr) && !IS_RTC_FAST_DRAM(addr) \
&& !IS_RTC_SLOW_DRAM(addr) && !IS_PADD(addr))
#define IS_MAPPING(addr) IS_IROM(addr) || IS_DROM(addr)
/****************************************************************************
* Private Types
****************************************************************************/
#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
extern uint8_t _image_irom_vma[];
extern uint8_t _image_irom_lma[];
extern uint8_t _image_irom_size[];
@ -106,16 +100,12 @@ extern uint8_t _image_irom_size[];
extern uint8_t _image_drom_vma[];
extern uint8_t _image_drom_lma[];
extern uint8_t _image_drom_size[];
#endif
/****************************************************************************
* ROM Function Prototypes
****************************************************************************/
#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
extern int ets_printf(const char *fmt, ...) printf_like(1, 2);
#endif
/****************************************************************************
* Private Functions
@ -253,7 +243,8 @@ int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
ets_printf("total segments stored %d\n", segments - 1);
#endif
#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
#if defined (CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESP32S3_APP_FORMAT_MCUBOOT)
ets_printf("IROM segment aligned lma 0x%08x vma 0x%08x len 0x%06x (%u)\n",
app_irom_start_aligned, app_irom_vaddr_aligned,
app_irom_size, app_irom_size);

8
arch/xtensa/src/esp32s2/loader.h → arch/xtensa/src/common/espressif/esp_loader.h
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/loader.h
* arch/xtensa/src/common/espressif/esp_loader.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -18,8 +18,8 @@
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_LOADER_H
#define __ARCH_XTENSA_SRC_ESP32S2_LOADER_H
#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_LOADER_H
#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_LOADER_H
/****************************************************************************
* Included Files
@ -77,4 +77,4 @@ int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_LOADER_H */
#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_LOADER_H */

2
arch/xtensa/src/esp32s2/Make.defs
View File

@ -29,7 +29,7 @@ HEAD_CSRC = esp32s2_start.c esp32s2_wdt.c
CHIP_CSRCS = esp32s2_allocateheap.c esp32s2_clockconfig.c esp32s2_irq.c
CHIP_CSRCS += esp32s2_gpio.c esp32s2_rtc_gpio.c esp32s2_region.c esp32s2_user.c
CHIP_CSRCS += esp32s2_timerisr.c esp32s2_lowputc.c esp32s2_systemreset.c
CHIP_CSRCS += esp32s2_dma.c esp32s2_libc_stubs.c loader.c
CHIP_CSRCS += esp32s2_dma.c esp32s2_libc_stubs.c
# Configuration-dependent ESP32-S2 files

8
arch/xtensa/src/esp32s2/esp32s2_start.c
View File

@ -42,7 +42,7 @@
#include "esp32s2_lowputc.h"
#include "esp32s2_wdt.h"
#include "esp32s2_rtc.h"
#include "loader.h"
#include "espressif/esp_loader.h"
#include "soc/extmem_reg.h"
#include "hal/mmu_hal.h"
@ -52,14 +52,8 @@
#include "hal/cache_hal.h"
#include "rom/spi_flash.h"
# include "bootloader_flash_priv.h"
# include "esp_rom_efuse.h"
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
# include "bootloader_init.h"
# include "bootloader_random.h"
# include "esp_rom_uart.h"
# include "esp_rom_sys.h"
# include "esp_app_format.h"
#endif
/****************************************************************************

212
arch/xtensa/src/esp32s3/esp32s3_start.c
View File

@ -49,6 +49,7 @@
#include "rom/esp32s3_libc_stubs.h"
#include "rom/opi_flash.h"
#include "rom/esp32s3_spiflash.h"
#include "espressif/esp_loader.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_types.h"
@ -61,10 +62,6 @@
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
# include "bootloader_init.h"
# include "bootloader_flash_priv.h"
# include "esp_rom_uart.h"
# include "esp_rom_sys.h"
# include "esp_app_format.h"
#endif
#include "esp_clk_internal.h"
@ -84,9 +81,6 @@
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
# ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
# define PRIMARY_SLOT_OFFSET CONFIG_ESP32S3_OTA_PRIMARY_SLOT_OFFSET
/* Cache MMU address mask (MMU tables ignore bits which are zero) */
# define MMU_FLASH_MASK (~(MMU_PAGE_SIZE - 1))
# else
/* Force offset to the beginning of the whole image */
@ -94,42 +88,6 @@
# endif
# define HDR_ATTR __attribute__((section(".entry_addr"))) \
__attribute__((used))
# define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */
# define CACHE_REG EXTMEM_ICACHE_CTRL1_REG
# define CACHE_MASK (EXTMEM_ICACHE_SHUT_IBUS_M | \
EXTMEM_ICACHE_SHUT_DBUS_M)
# define CHECKSUM_ALIGN 16
# define IS_PADD(addr) (addr == 0)
# define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH)
# define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH)
# define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH)
# define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH)
# define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr))
# define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr))
# ifdef SOC_RTC_FAST_MEM_SUPPORTED
# define IS_RTC_FAST_IRAM(addr) \
(addr >= SOC_RTC_IRAM_LOW && addr < SOC_RTC_IRAM_HIGH)
# define IS_RTC_FAST_DRAM(addr) \
(addr >= SOC_RTC_DRAM_LOW && addr < SOC_RTC_DRAM_HIGH)
# else
# define IS_RTC_FAST_IRAM(addr) 0
# define IS_RTC_FAST_DRAM(addr) 0
# endif
# ifdef SOC_RTC_SLOW_MEM_SUPPORTED
# define IS_RTC_SLOW_DRAM(addr) \
(addr >= SOC_RTC_DATA_LOW && addr < SOC_RTC_DATA_HIGH)
# else
# define IS_RTC_SLOW_DRAM(addr) 0
# endif
# define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \
&& !IS_IRAM(addr) && !IS_DRAM(addr) \
&& !IS_RTC_FAST_IRAM(addr) && !IS_RTC_FAST_DRAM(addr) \
&& !IS_RTC_SLOW_DRAM(addr) && !IS_PADD(addr))
# define IS_MAPPING(addr) IS_IROM(addr) || IS_DROM(addr)
#endif
/****************************************************************************
@ -474,174 +432,6 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void)
for (; ; ); /* Should not return */
}
/****************************************************************************
* Name: map_rom_segments
*
* Description:
* Configure the MMU and Cache peripherals for accessing ROM code and data.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \
defined(CONFIG_ESPRESSIF_SIMPLE_BOOT)
static int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
uint32_t app_drom_size, uint32_t app_irom_start,
uint32_t app_irom_vaddr, uint32_t app_irom_size)
{
uint32_t rc = 0;
uint32_t actual_mapped_len = 0;
uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK;
uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK;
uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK;
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
esp_image_header_t image_header; /* Header for entire image */
esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr;
bool padding_checksum = false;
unsigned int segments = 0;
unsigned int ram_segments = 0;
unsigned int rom_segments = 0;
size_t offset = CONFIG_BOOTLOADER_OFFSET_IN_FLASH;
/* Read image header */
if (bootloader_flash_read(offset, &image_header,
sizeof(esp_image_header_t),
true) != ESP_OK)
{
ets_printf("Failed to load image header!\n");
abort();
}
offset += sizeof(esp_image_header_t);
/* Iterate for segment information parsing */
while (segments++ < 16 && rom_segments < 2)
{
/* Read segment header */
if (bootloader_flash_read(offset, &segment_hdr,
sizeof(esp_image_segment_header_t),
true) != ESP_OK)
{
ets_printf("failed to read segment header at %x\n", offset);
abort();
}
if (IS_NONE(segment_hdr.load_addr))
{
break;
}
if (IS_RTC_FAST_IRAM(segment_hdr.load_addr) ||
IS_RTC_FAST_DRAM(segment_hdr.load_addr) ||
IS_RTC_SLOW_DRAM(segment_hdr.load_addr))
{
/* RTC segment is loaded by ROM bootloader */
ram_segments++;
}
ets_printf("%s: lma 0x%08x vma 0x%08x len 0x%-6x (%u)\n",
IS_NONE(segment_hdr.load_addr) ? "???" :
IS_RTC_FAST_IRAM(segment_hdr.load_addr) ||
IS_RTC_FAST_DRAM(segment_hdr.load_addr) ||
IS_RTC_SLOW_DRAM(segment_hdr.load_addr) ? "rtc" :
IS_MMAP(segment_hdr.load_addr) ?
IS_IROM(segment_hdr.load_addr) ? "imap" : "dmap" :
IS_PADD(segment_hdr.load_addr) ? "padd" :
IS_DRAM(segment_hdr.load_addr) ? "dram" : "iram",
offset + sizeof(esp_image_segment_header_t),
segment_hdr.load_addr, segment_hdr.data_len,
segment_hdr.data_len);
/* Fix drom and irom produced be the linker, as this
* is later invalidated by the elf2image command.
*/
if (IS_DROM(segment_hdr.load_addr) &&
segment_hdr.load_addr == (uint32_t)_image_drom_vma)
{
app_drom_start = offset + sizeof(esp_image_segment_header_t);
app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
rom_segments++;
}
if (IS_IROM(segment_hdr.load_addr) &&
segment_hdr.load_addr == (uint32_t)_image_irom_vma)
{
app_irom_start = offset + sizeof(esp_image_segment_header_t);
app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK;
rom_segments++;
}
if (IS_SRAM(segment_hdr.load_addr))
{
ram_segments++;
}
offset += sizeof(esp_image_segment_header_t) + segment_hdr.data_len;
if (ram_segments == image_header.segment_count && !padding_checksum)
{
offset += (CHECKSUM_ALIGN - 1) - (offset % CHECKSUM_ALIGN) + 1;
padding_checksum = true;
}
}
if (segments == 0 || segments == 16)
{
ets_printf("Error parsing segments\n");
}
ets_printf("total segments stored %d\n", segments - 1);
#endif
cache_hal_disable(CACHE_TYPE_ALL);
/* Clear the MMU entries that are already set up,
* so the new app only has the mappings it creates.
*/
mmu_hal_unmap_all();
mmu_hal_map_region(0, MMU_TARGET_FLASH0,
app_drom_vaddr_aligned, app_drom_start_aligned,
app_drom_size, &actual_mapped_len);
mmu_hal_map_region(0, MMU_TARGET_FLASH0,
app_irom_vaddr_aligned, app_irom_start_aligned,
app_irom_size, &actual_mapped_len);
/* ------------------Enable corresponding buses--------------------- */
cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned,
app_drom_size);
cache_ll_l1_enable_bus(0, bus_mask);
bus_mask = cache_ll_l1_get_bus(0, app_irom_vaddr_aligned, app_irom_size);
cache_ll_l1_enable_bus(0, bus_mask);
#if CONFIG_ESPRESSIF_NUM_CPUS > 1
bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_aligned, app_drom_size);
cache_ll_l1_enable_bus(1, bus_mask);
bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_aligned, app_irom_size);
cache_ll_l1_enable_bus(1, bus_mask);
#endif
/* ------------------Enable Cache----------------------------------- */
cache_hal_enable(CACHE_TYPE_ALL);
return (int)rc;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/

10
boards/xtensa/esp32s2/common/scripts/mcuboot_sections.ld
View File

@ -62,11 +62,13 @@ SECTIONS
.flash.rodata :
{
_srodata = ABSOLUTE(.);
*(EXCLUDE_FILE (esp32s2_start.* loader.* esp32s2_region.*
*(EXCLUDE_FILE (esp32s2_start.* esp32s2_region.*
*libarch.a:*esp_loader.*
*libarch.a:esp32s2_spiflash.*
*libarch.a:*cache_hal.* *libarch.a:*mmu_hal.*
*libarch.a:*mpu_hal.*) .rodata)
*(EXCLUDE_FILE (esp32s2_start.* loader.* esp32s2_region.*
*(EXCLUDE_FILE (esp32s2_start.* esp32s2_region.*
*libarch.a:*esp_loader.*
*libarch.a:esp32s2_spiflash.*
*libarch.a:*cache_hal.* *libarch.a:*mmu_hal.*
*libarch.a:*mpu_hal.*) .rodata.*)
@ -168,8 +170,8 @@ SECTIONS
*(.iram1 .iram1.*)
esp32s2_start.*(.literal .text .literal.* .text.*)
esp32s2_region.*(.text .text.* .literal .literal.*)
loader.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_loader.*(.text .text.* .literal .literal.*)
*libarch.a:esp32s2_spiflash.*(.literal .text .literal.* .text.*)
*libarch.a:*cache_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
@ -248,8 +250,8 @@ SECTIONS
*(.dram1 .dram1.*)
esp32s2_start.*(.rodata .rodata.*)
esp32s2_region.*(.rodata .rodata.*)
loader.*(.rodata .rodata.*)
*libarch.a:*esp_loader.*(.rodata .rodata.*)
*libarch.a:esp32s2_spiflash.*(.rodata .rodata.*)
*libarch.a:*cache_hal.*(.rodata .rodata.*)
*libarch.a:*uart_hal.*(.rodata .rodata.*)

6
boards/xtensa/esp32s2/common/scripts/simple_boot_sections.ld
View File

@ -74,8 +74,8 @@ SECTIONS
. = ALIGN (4);
esp32s2_start.*(.literal .text .literal.* .text.*)
esp32s2_region.*(.text .text.* .literal .literal.*)
loader.*(.literal .text .literal.* .text.*)
*libarch.a:*esp_loader.*(.literal .text .literal.* .text.*)
*libarch.a:*brownout_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*cpu.*(.text .text.* .literal .literal.*)
*libarch.a:*gpio_hal.*(.text .text.* .literal .literal.*)
@ -216,8 +216,8 @@ SECTIONS
*(.dram1 .dram1.*)
esp32s2_start.*(.rodata .rodata.*)
esp32s2_region.*(.rodata .rodata.*)
loader.*(.rodata .rodata.*)
*libarch.a:*esp_loader.*(.rodata .rodata.*)
*libarch.a:*brownout.*(.rodata .rodata.*)
*libarch.a:*cpu.*(.rodata .rodata.*)
*libarch.a:*gpio_hal.*(.rodata .rodata.*)
@ -361,7 +361,7 @@ SECTIONS
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma;
/* The alignment of the ".flash.text" output section is forced to
* 0x0000FFFF (64KB) to ensure that it will be allocated at the beginning
* 0x00010000 (64KB) to ensure that it will be allocated at the beginning
* of the next available Flash block.
* This is required to meet the following constraint from the external
* flash MMU:

16
boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld
View File

@ -66,8 +66,16 @@ SECTIONS
_rodata_reserved_start = .;
_srodata = ABSOLUTE(.);
*(EXCLUDE_FILE (esp32s3_start.*) .rodata)
*(EXCLUDE_FILE (esp32s3_start.*) .rodata.*)
*(EXCLUDE_FILE (esp32s3_start.* esp32s3_region.*
*libarch.a:*esp_loader.*
*libarch.a:esp32s3_spiflash.*
*libarch.a:*cache_hal.* *libarch.a:*mmu_hal.*
*libarch.a:*mpu_hal.*) .rodata)
*(EXCLUDE_FILE (esp32s3_start.* esp32s3_region.*
*libarch.a:*esp_loader.*
*libarch.a:esp32s3_spiflash.*
*libarch.a:*cache_hal.* *libarch.a:*mmu_hal.*
*libarch.a:*mpu_hal.*) .rodata.*)
#ifdef CONFIG_ESP32S3_WIRELESS
*(.rodata_wlog_verbose.*)
@ -172,7 +180,9 @@ SECTIONS
*(.iram1 .iram1.*)
esp32s3_start.*(.literal .text .literal.* .text.*)
esp32s3_region.*(.literal .text .literal.* .text.*)
*libarch.a:*esp_loader.*(.text .text.* .literal .literal.*)
*libarch.a:esp32s3_cpuindex.*(.literal .text .literal.* .text.*)
*libarch.a:esp32s3_irq.*(.literal .text .literal.* .text.*)
*libarch.a:esp32s3_user.*(.literal .text .literal.* .text.*)
@ -319,8 +329,10 @@ SECTIONS
KEEP (*(.jcr))
*(.dram1 .dram1.*)
esp32s3_start.*(.rodata .rodata.*)
esp32s3_region.*(.rodata .rodata.*)
*libphy.a:(.rodata .rodata.*)
*libarch.a:*esp_loader.*(.rodata .rodata.*)
*libarch.a:xtensa_context.*(.rodata .rodata.*)
*libarch.a:esp32s3_spiflash.*(.rodata .rodata.*)
*libarch.a:*cache_hal.*(.rodata .rodata.*)

4
boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld
View File

@ -77,7 +77,9 @@ SECTIONS
*(.iram1 .iram1.*)
esp32s3_start.*(.literal .text .literal.* .text.*)
esp32s3_region.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_loader.*(.literal .text .literal.* .text.*)
*libarch.a:esp32s3_cpuindex.*(.literal .text .literal.* .text.*)
*libarch.a:esp32s3_irq.*(.literal .text .literal.* .text.*)
*libarch.a:esp32s3_user.*(.literal .text .literal.* .text.*)
@ -284,6 +286,7 @@ SECTIONS
KEEP (*(.jcr))
*(.dram1 .dram1.*)
esp32s3_start.*(.rodata .rodata.*)
esp32s3_region.*(.rodata .rodata.*)
*libphy.a:(.rodata .rodata.*)
*libarch.a:xtensa_context.*(.rodata .rodata.*)
@ -294,6 +297,7 @@ SECTIONS
#endif
*libsched.a:*sched_get_stackinfo.*(.rodata .rodata.*)
*libarch.a:*esp_loader.*(.rodata .rodata.*)
*libarch.a:esp32s3_spiflash.*(.rodata .rodata.*)
*libarch.a:*brownout.*(.rodata .rodata.*)
*libarch.a:*cpu.*(.rodata .rodata.*)