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arch/risc-v: Remove dupped irq code from rv32m1 

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-01-20 23:08:24 +08:00 committed by Xiang Xiao
parent 089dc2e090
commit 6dc4dd207f
4 changed files with 4 additions and 58 deletions
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33
arch/risc-v/include/mpfs/irq.h
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@ -33,38 +33,7 @@
/* Map RISC-V exception code to NuttX IRQ */
/* IRQ 0-15 : (exception:interrupt=0) */
#define MPFS_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */
#define MPFS_IRQ_IAFAULT (1) /* Instruction Address Fault */
#define MPFS_IRQ_IINSTRUCTION (2) /* Illegal Instruction */
#define MPFS_IRQ_BPOINT (3) /* Break Point */
#define MPFS_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */
#define MPFS_IRQ_LAFAULT (5) /* Load Access Fault */
#define MPFS_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */
#define MPFS_IRQ_SAFAULT (7) /* Store/AMO Access Fault */
#define MPFS_IRQ_ECALLU (8) /* Environment Call from U-mode */
#define MPFS_IRQ_ECALLS (9) /* Environment Call from S-mode */
#define MPFS_IRQ_ECALLH (10) /* Environment Call from H-mode */
#define MPFS_IRQ_ECALLM (11) /* Environment Call from M-mode */
#define MPFS_IRQ_INSTRUCTIONPF (12) /* Instruction page fault */
#define MPFS_IRQ_LOADPF (13) /* Load page fault */
#define MPFS_IRQ_RESERVED (14) /* Reserved */
#define MPFS_IRQ_SROREPF (15) /* Store/AMO page fault */
/* IRQ 16- : (async event:interrupt=1) */
#define MPFS_IRQ_ASYNC (16)
#define MPFS_IRQ_SSOFT (MPFS_IRQ_ASYNC + 1) /* Supervisor Software Int */
#define MPFS_IRQ_MSOFT (MPFS_IRQ_ASYNC + 3) /* Machine Software Int */
#define MPFS_IRQ_STIMER (MPFS_IRQ_ASYNC + 5) /* Supervisor Timer Int */
#define MPFS_IRQ_MTIMER (MPFS_IRQ_ASYNC + 7) /* Machine Timer Int */
#define MPFS_IRQ_SEXT (MPFS_IRQ_ASYNC + 9) /* Supervisor External Int */
#define MPFS_IRQ_MEXT (MPFS_IRQ_ASYNC + 11) /* Machine External Int */
/* IRQ 32-79 : 47 Local interrupts. */
#define MPFS_IRQ_LOCAL_START (MPFS_IRQ_ASYNC + 16)
#define MPFS_IRQ_LOCAL_START (RISCV_IRQ_ASYNC + 16)
#define MPFS_IRQ_LOCAL_0 (MPFS_IRQ_LOCAL_START + 0) /* Local 0 spare */
#define MPFS_IRQ_LOCAL_1 (MPFS_IRQ_LOCAL_START + 1) /* Local 1 spare */
#define MPFS_IRQ_LOCAL_2 (MPFS_IRQ_LOCAL_START + 2) /* Local 2 spare */

25
arch/risc-v/include/rv32m1/rv32m1ri5cy_irq.h
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@ -31,32 +31,9 @@
* Pre-processor Definitions
****************************************************************************/
/* RV32M1 RI5CY CPU throws four exceptions:
* -Reset,
* -Illegal Instruction,
* -ECALL Instruct Excecuted,
* -Load Store Unit Error. MCAUSE must be checked to
* figure out what kind of Error.
*/
/* RISC-V standard exceptions alias with prefix RV32M1 **********************/
#define RV32M1_IRQ_ADDE_MISALIGNED MCAUSE_ADDE_MISALIGNED
#define RV32M1_IRQ_INST_ACCESS_FAULT MCAUSE_INST_ACCESS_FAULT
#define RV32M1_IRQ_ILLEGAL_INST MCAUSE_ILLEGAL_INST
#define RV32M1_IRQ_LOAD_MISALIGNED MCAUSE_LOAD_MISALIGNED
#define RV32M1_IRQ_LOAD_ACCESS_FAULT MCAUSE_LOAD_ACCESS_FAULT
#define RV32M1_IRQ_STORE_MISALIGNED MCAUSE_STORE_MISALIGNED
#define RV32M1_IRQ_STORE_ACCESS_FAULT MCAUSE_STORE_ACCESS_FAULT
#define RV32M1_IRQ_ECALL_U MCAUSE_ECALL_U
#define RV32M1_IRQ_ECALL_M MCAUSE_ECALL_M
/* RV32M1 RI5CY Interrupts **************************************************/
/* IRQ 16- : (async event:interrupt=1) */
#define RV32M1_IRQ_ASYNC (16)
#define RV32M1_IRQ_MEXT (RV32M1_IRQ_ASYNC + 0) /* Machine External Int */
#define RV32M1_IRQ_MEXT (RISCV_IRQ_ASYNC + 0) /* Machine External Int */
/* Machine Global External Interrupt */

2
arch/risc-v/src/rv32m1/rv32m1_irq.c
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@ -117,7 +117,7 @@ void up_irqinitialize(void)
/* Attach the ecall interrupt handler */
irq_attach(RV32M1_IRQ_ECALL_M, riscv_swint, NULL);
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
#ifndef CONFIG_SUPPRESS_INTERRUPTS

2
arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c
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@ -63,7 +63,7 @@ void *rv32m1_dispatch_irq(uintptr_t vector, uintptr_t *regs)
/* NOTE: In case of ecall, we need to adjust mepc in the context */
if (RV32M1_IRQ_ECALL_M == irq)
if (RISCV_IRQ_ECALLM == irq)
{
*mepc += 4;
}