bcm43xxx: supported high-speed timing mode with a clock rate up to 50MHz

drivers/wireless/ieee80211/bcm43xxx/Kconfig

@@ -116,4 +116,11 @@ config IEEE80211_BROADCOM_FRAME_POOL_SIZE
 		This parameter sets the size of the shared SDPCM frame pool
 		used for both RX and TX transfers.
 
+config IEEE80211_BROADCOM_SDIO_EHS_MODE
+	bool "High-Speed Mode over SDIO"
+	default n
+	---help---
+		This selection enables High-Speed timing mode
+		with a clock rate up to 50MHz.
+
 endif # IEEE80211_BROADCOM_FULLMAC

drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.c

@@ -208,6 +208,9 @@ int bcmf_sdio_bus_sleep(FAR struct bcmf_sdio_dev_s *sbus, bool sleep)
 int bcmf_probe(FAR struct bcmf_sdio_dev_s *sbus)
 {
   int ret;
+#ifdef CONFIG_IEEE80211_BROADCOM_SDIO_EHS_MODE
+  uint8_t value;
+#endif
 
   /* Probe sdio card compatible device */
 
@@ -246,10 +249,28 @@ int bcmf_probe(FAR struct bcmf_sdio_dev_s *sbus)
       goto exit_error;
     }
 
-  /* Default device clock speed is up to 25 MHz
+#ifdef CONFIG_IEEE80211_BROADCOM_SDIO_EHS_MODE
+  /* Default device clock speed is up to 25 MHz.
    * We could set EHS bit to operate at a clock rate up to 50 MHz.
    */
 
+  ret = bcmf_read_reg(sbus, 0, SDIO_CCCR_HIGHSPEED, &value);
+
+  if (ret & SDIO_CCCR_HIGHSPEED_SHS)
+    {
+      /* If the chip confirms its High-Speed capability,
+       * enable the High-Speed mode.
+       */
+
+      ret = bcmf_write_reg(sbus, 0, SDIO_CCCR_HIGHSPEED,
+                           SDIO_CCCR_HIGHSPEED_EHS);
+    }
+  else
+    {
+      wlwarn("High-Speed mode is not supported by the chip!\n", value);
+    }
+#endif
+
   SDIO_CLOCK(sbus->sdio_dev, CLOCK_SD_TRANSFER_4BIT);
   up_mdelay(BCMF_CLOCK_SETUP_DELAY_MS);
 

include/nuttx/sdio.h

@@ -408,6 +408,9 @@
 #define SDIO_CCCR_BUS_IF_1_BIT           0x01 /* 1 bit bus width setting   */
 #define SDIO_CCCR_BUS_IF_4_BITS          0x02 /* 4 bits bus width setting  */
 
+#define SDIO_CCCR_HIGHSPEED_SHS          0x01 /* High-Speed mode capability */
+#define SDIO_CCCR_HIGHSPEED_EHS          0x02 /* Enable High-Speed mode    */
+
 #define SDIO_FBR_SHIFT   8                     /* FBR bit shift            */
 #define SDIO_FN1_BR_BASE (1 << SDIO_FBR_SHIFT) /* Func 1 registers base    */
 #define SDIO_FN2_BR_BASE (2 << SDIO_FBR_SHIFT) /* Func 2 registers base    */