risc-v: Make exception_common 8 byte align

Some SoC like bl602 require the exception entry 8 byte align, it should be safe for other chips so we can apply it globally. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-17 10:21:10 +08:00 · 2022-01-17 10:21:10 +08:00 · 676d35f007
parent 0f080cdeaf
commit 676d35f007
1 changed files with 1 additions and 0 deletions
--- a/arch/risc-v/src/common/riscv_exception_common.S
+++ b/arch/risc-v/src/common/riscv_exception_common.S
@ -43,6 +43,7 @@

  .section .text
  .global exception_common
+  .align  8

 exception_common: