diff --git a/arch/arm/src/samdl/sam_serial.c b/arch/arm/src/samdl/sam_serial.c
index 66ec49c5de..a5c5bccbe4 100644
--- a/arch/arm/src/samdl/sam_serial.c
+++ b/arch/arm/src/samdl/sam_serial.c
@@ -977,9 +977,9 @@ void up_earlyserialinit(void)
   sam_disableallints(TTYS5_DEV.priv);
 #endif
 
+#ifdef HAVE_SERIAL_CONSOLE
   /* Mark the serial console (if any) */
 
-#ifdef HAVE_SERIAL_CONSOLE
   CONSOLE_DEV.isconsole = true;
 #endif
 }
diff --git a/arch/arm/src/samdl/saml_clockconfig.c b/arch/arm/src/samdl/saml_clockconfig.c
index edb86611cf..b428db467f 100644
--- a/arch/arm/src/samdl/saml_clockconfig.c
+++ b/arch/arm/src/samdl/saml_clockconfig.c
@@ -277,6 +277,23 @@ static const struct sam_gclkconfig_s g_gclkconfig[] =
     .clksrc     = (uint8_t)(BOARD_GCLK7_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
   }
 #endif
+
+  /* GCLK generator 8 */
+
+#ifdef BOARD_GCLK8_ENABLE
+  ,
+  {
+    .gclk       = 8,
+#ifdef BOARD_GCLK8_RUN_IN_STANDBY
+    .runstandby = true;
+#endif
+#ifdef BOARD_GCLK8_OUTPUT_ENABLE
+    .output     = true;
+#endif
+    .prescaler  = BOARD_GCLK8_PRESCALER,
+    .clksrc     = (uint8_t)(BOARD_GCLK8_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
+  }
+#endif
 };
 
 #define NGCLKS_ENABLED (sizeof(g_gclkconfig) / sizeof(struct sam_gclkconfig_s))
diff --git a/configs/saml21-xplained/include/board.h b/configs/saml21-xplained/include/board.h
index a721c7e327..3b2934be3b 100644
--- a/configs/saml21-xplained/include/board.h
+++ b/configs/saml21-xplained/include/board.h
@@ -166,7 +166,7 @@
  * DFLL output frequency (Fdfll) is given by:
  *
  *  Fdfll = DFLLmul * Frefclk
- *        = 6 * 8000000 = 48MHz
+ *        = 12 * 4000000 = 48MHz
  *
  * Where the reference clock is Generic Clock Channel 0 output of GLCK1.
  * GCLCK1 provides OSC16M, undivided.
@@ -224,7 +224,7 @@
 #define BOARD_DFLL48M_MAXCOARSESTEP      (0x1f / 4)
 #define BOARD_DFLL48M_MAXFINESTEP        (0xff / 4)
 
-#define BOARD_DFLL48M_FREQUENCY          (48000000)
+#define BOARD_DFLL48M_FREQUENCY          (BOARD_DFLL48M_MULTIPLIER * BOARD_OSC16M_FREQUENCY)
 
 /* Fractional Digital Phase Locked Loop configuration.
  *
@@ -248,18 +248,18 @@
 
 #undef  BOARD_FDPLL96M_ENABLE
 #undef  BOARD_FDPLL96M_RUNINSTDBY
-#define BOARD_FDPLL96M_ONDEMAND           1
+#define BOARD_FDPLL96M_ONDEMAND          1
 #undef  BOARD_FDPLL96M_LBYPASS
 #undef  BOARD_FDPLL96M_WUF
 #undef  BOARD_FDPLL96M_LPEN
-#define BOARD_FDPLL96M_FILTER             OSCCTRL_DPLLCTRLB_FILTER_DEFAULT
-#define BOARD_FDPLL96M_REFCLK             OSCCTRL_DPLLCTRLB_REFLCK_XOSCK32K
-#define BOARD_FDPLL96M_REFCLK_CLKGEN      1
+#define BOARD_FDPLL96M_FILTER            OSCCTRL_DPLLCTRLB_FILTER_DEFAULT
+#define BOARD_FDPLL96M_REFCLK            OSCCTRL_DPLLCTRLB_REFLCK_XOSCK32K
+#define BOARD_FDPLL96M_REFCLK_CLKGEN     1
 #undef  BOARD_FDPLL96M_LOCKTIME_ENABLE
-#define BOARD_FDPLL96M_LOCKTIME           OSCCTRL_DPLLCTRLB_LTIME_NONE
-#define BOARD_FDPLL96M_LOCKTIME_CLKGEN    1
-#define BOARD_FDPLL96M_REFDIV             1
-#define BOARD_FDPLL96M_PRESCALER          OSCCTRL_DPLLPRESC_DIV1
+#define BOARD_FDPLL96M_LOCKTIME          OSCCTRL_DPLLCTRLB_LTIME_NONE
+#define BOARD_FDPLL96M_LOCKTIME_CLKGEN   1
+#define BOARD_FDPLL96M_REFDIV            1
+#define BOARD_FDPLL96M_PRESCALER         OSCCTRL_DPLLPRESC_DIV1
 
 #define BOARD_FDPLL96M_REFFREQ           32768
 #define BOARD_FDPLL96M_FREQUENCY         48000000
@@ -353,6 +353,15 @@
 #undef  BOARD_GCLK7_OUTPUT_ENABLE
 #define BOARD_GCLK7_FREQUENCY         (BOARD_OSC16M_FREQUENCY / BOARD_GCLK7_PRESCALER)
 
+/* Configure GCLK generator 8 */
+
+#undef  BOARD_GCLK8_ENABLE
+#undef  BOARD_GCLK8_RUN_IN_STANDBY
+#define BOARD_GCLK8_CLOCK_SOURCE      GCLK_GENCTRL_SRC_OSC16M
+#define BOARD_GCLK8_PRESCALER         1
+#undef  BOARD_GCLK8_OUTPUT_ENABLE
+#define BOARD_GCLK8_FREQUENCY         (BOARD_OSC16M_FREQUENCY / BOARD_GCLK8_PRESCALER)
+
 /* The source of the main clock is always GCLK_MAIN.  Also called GCLKGEN[0], this is
  * the clock feeding the Power Manager. The Power Manager, in turn, generates main
  * clock which is divided down to produce the CPU, AHB, and APB clocks.