alarm 10 now runs to completion
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@ -178,7 +178,6 @@ static void stm32_alarm_callback(FAR void *arg, unsigned int alarmid)
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rtc_alarm_callback_t cb;
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FAR void *priv;
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DEBUGASSERT(priv != NULL);
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DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB);
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lower = (struct stm32_lowerhalf_s *)arg;
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@ -190,6 +189,7 @@ static void stm32_alarm_callback(FAR void *arg, unsigned int alarmid)
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cb = (rtc_alarm_callback_t)cbinfo->cb;
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priv = (FAR void *)cbinfo->priv;
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DEBUGASSERT(priv != NULL);
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cbinfo->cb = NULL;
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cbinfo->priv = NULL;
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@ -219,7 +219,7 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg);
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#ifdef CONFIG_DEBUG_RTC
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static void rtc_dumpregs(FAR const char *msg)
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{
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rtclldbg("%s:\n", msg);
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rtclldbg("*** %s:\n", msg);
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rtclldbg(" TR: %08x\n", getreg32(STM32_RTC_TR));
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rtclldbg(" DR: %08x\n", getreg32(STM32_RTC_DR));
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rtclldbg(" CR: %08x\n", getreg32(STM32_RTC_CR));
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@ -240,6 +240,12 @@ static void rtc_dumpregs(FAR const char *msg)
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rtclldbg("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR));
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rtclldbg("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR));
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rtclldbg("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG));
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int rtc_state =
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((getreg32(STM32_EXTI_RTSR) & EXTI_RTC_ALARM) ? 0x1000 : 0) |
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((getreg32(STM32_EXTI_FTSR) & EXTI_RTC_ALARM) ? 0x0100 : 0) |
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((getreg32(STM32_EXTI_IMR) & EXTI_RTC_ALARM) ? 0x0010 : 0) |
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((getreg32(STM32_EXTI_EMR) & EXTI_RTC_ALARM) ? 0x0001 : 0);
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rtclldbg("EXTI (RTSR FTSR ISR EVT): %01x\n",rtc_state);
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}
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#else
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# define rtc_dumpregs(msg)
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@ -600,9 +606,9 @@ static void rtc_resume(void)
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regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF);
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putreg32(regval, STM32_RTC_ISR);
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/* Clear the EXTI Line 17 Pending bit (Connected internally to RTC Alarm) */
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/* Clear the RTC Alarm Pending bit */
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putreg32((1 << 17), STM32_EXTI_PR);
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putreg32((1 << EXTI_RTC_ALARM ), STM32_EXTI_PR);
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#endif
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}
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@ -876,8 +882,6 @@ int up_rtc_initialize(void)
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* maximum performance.
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*/
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rtc_dumpregs("On reset");
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/* Select the clock source */
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/* Save the token before losing it when resetting */
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@ -902,16 +906,19 @@ int up_rtc_initialize(void)
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#ifdef CONFIG_RTC_HSECLOCK
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/* Use the HSE clock as the input to the RTC block */
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rtc_dumpregs("On reset HSE");
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modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE);
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#elif defined(CONFIG_RTC_LSICLOCK)
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/* Use the LSI clock as the input to the RTC block */
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rtc_dumpregs("On reset LSI");
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modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI);
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#elif defined(CONFIG_RTC_LSECLOCK)
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/* Use the LSE clock as the input to the RTC block */
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rtc_dumpregs("On reset LSE");
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modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE);
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#endif
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@ -926,6 +933,8 @@ int up_rtc_initialize(void)
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uint32_t clksrc = getreg32(STM32_RCC_XXX);
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rtc_dumpregs("On reset warm");
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#if defined(CONFIG_RTC_HSECLOCK)
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if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_HSE)
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#elif defined(CONFIG_RTC_LSICLOCK)
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@ -1060,10 +1069,13 @@ int up_rtc_initialize(void)
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*/
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stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler);
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rtc_dumpregs("After InitExtiAlarm");
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#else
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rtc_dumpregs("After Initialization");
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#endif
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g_rtc_enabled = true;
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rtc_dumpregs("After Initialization");
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return OK;
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}
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@ -1365,13 +1377,14 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
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cbinfo->ac_cb = alminfo->as_cb;
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cbinfo->ac_arg = alminfo->as_arg;
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ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE);
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ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE | RTC_ALRMR_DIS_DATE_MASK);
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if (ret < 0)
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{
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cbinfo->ac_cb = NULL;
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cbinfo->ac_arg = NULL;
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}
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}
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rtc_dumpregs("Set AlarmA");
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break;
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case RTC_ALARMB:
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@ -1380,13 +1393,14 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
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cbinfo->ac_cb = alminfo->as_cb;
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cbinfo->ac_arg = alminfo->as_arg;
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ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE);
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ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE | RTC_ALRMR_DIS_DATE_MASK);
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if (ret < 0)
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{
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cbinfo->ac_cb = NULL;
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cbinfo->ac_arg = NULL;
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}
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}
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rtc_dumpregs("Set AlarmB");
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break;
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default:
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@ -1486,7 +1500,7 @@ int stm32_rtc_cancelalarm(enum alm_id_e alarmid)
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break;
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default:
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rtcvdbg("ERROR: Invalid ALARM%d\n", alminfo->as_id);
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rtcvdbg("ERROR: Invalid ALARM%d\n", alarmid);
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break;
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}
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