Merged in raiden00/nuttx (pull request #510)
Initial ADC support for the STM32F33XX * stm32_adc.h: add JEXTSEL definitions and hrtim trigger configuration * stm32_adc.c: move STM32F33 ADC logic to a separate file Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni
Gregory Nutt
parent
566ad9e5f9
commit
61293cfc4c
|
|
@ -206,8 +206,12 @@ endif
|
|||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32_ADC),y)
|
||||
ifeq ($(CONFIG_STM32_STM32F33XX),y)
|
||||
CHIP_CSRCS += stm32f33xxx_adc.c
|
||||
else
|
||||
CHIP_CSRCS += stm32_adc.c
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32_SDADC),y)
|
||||
CHIP_CSRCS += stm32_sdadc.c
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@
|
|||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Diego Sanchez <dsanchez@nx-engineering.com>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
* Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -81,9 +80,8 @@
|
|||
/* This implementation is for the STM32 F1, F2, F3, F4 and STM32L15XX only */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \
|
||||
defined(CONFIG_STM32_STM32L15XX)
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
|
||||
defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
|
||||
/* At the moment there is no proper implementation for timers external
|
||||
* trigger in STM32L15XX May be added latter
|
||||
|
|
@ -93,14 +91,6 @@
|
|||
# warning "There is no proper implementation for TIMER TRIGGERS at the moment"
|
||||
#endif
|
||||
|
||||
/* At the moment there is no proper implementation for HRTIMER external
|
||||
* trigger in STM32F33XX
|
||||
*/
|
||||
|
||||
#if defined(ADC_HAVE_HRTIMER) && defined(CONFIG_STM32_STM32F33XX)
|
||||
# warning "There is no proper implementation for HRTIMER TRIGGERS at the moment"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
|
@ -118,10 +108,6 @@
|
|||
# define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST
|
||||
# define RCC_RSTR_ADC3RST RCC_AHBRSTR_ADC34RST
|
||||
# define RCC_RSTR_ADC4RST RCC_AHBRSTR_ADC34RST
|
||||
#elif defined(CONFIG_STM32_STM32F33XX)
|
||||
# define STM32_RCC_RSTR STM32_RCC_AHBRSTR
|
||||
# define RCC_RSTR_ADC1RST RCC_AHBRSTR_ADC12RST
|
||||
# define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST
|
||||
#elif defined(CONFIG_STM32_STM32F37XX)
|
||||
# define STM32_RCC_RSTR STM32_RCC_APB2RSTR
|
||||
# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST
|
||||
|
|
@ -138,7 +124,7 @@
|
|||
|
||||
/* ADC interrupts ***********************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR_OFFSET
|
||||
# define ADC_DMAREG_DMA ADC_CFGR_DMAEN
|
||||
# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR_OFFSET
|
||||
|
|
@ -240,7 +226,7 @@
|
|||
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \
|
||||
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \
|
||||
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT))
|
||||
#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
#elif defined(CONFIG_STM32_STM32F30XX)
|
||||
# if defined(ADC_HAVE_DMA) || (ADC_MAX_SAMPLES == 1)
|
||||
# define ADC_SMPR_DEFAULT ADC_SMPR_61p5
|
||||
# else /* Slow down sampling frequency */
|
||||
|
|
@ -352,8 +338,8 @@ struct stm32_dev_s
|
|||
/* ADC Register access */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \
|
||||
defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \
|
||||
defined(CONFIG_STM32_STM32L15XX)
|
||||
static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
|
||||
uint32_t setbits);
|
||||
#endif
|
||||
|
|
@ -620,8 +606,8 @@ static struct adc_dev_s g_adcdev4 =
|
|||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \
|
||||
defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \
|
||||
defined(CONFIG_STM32_STM32L15XX)
|
||||
static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
|
||||
uint32_t setbits)
|
||||
{
|
||||
|
|
@ -1256,7 +1242,7 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
|
|||
|
||||
adc_enable(priv, true);
|
||||
}
|
||||
#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
#elif defined(CONFIG_STM32_STM32F30XX)
|
||||
static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
|
@ -1534,7 +1520,7 @@ static void adc_select_ch_bank(FAR struct stm32_dev_s *priv,
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
static void adc_enable(FAR struct stm32_dev_s *priv, bool enable)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
|
@ -1765,7 +1751,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
|||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
|
||||
/* Turn off the ADC so we can write the RCC bits */
|
||||
|
||||
|
|
@ -1781,7 +1767,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
|||
|
||||
adc_rccreset(priv, false);
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
|
||||
/* Set voltage regular enable to intermediate state */
|
||||
|
||||
|
|
@ -1836,7 +1822,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
|||
adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
|
||||
/* Enable the analog watchdog */
|
||||
|
||||
|
|
@ -1884,7 +1870,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
|||
|
||||
adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits);
|
||||
|
||||
#else /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM33XX */
|
||||
#else /* CONFIG_STM32_STM32F30XX */
|
||||
|
||||
/* Enable the analog watchdog */
|
||||
|
||||
|
|
@ -1982,7 +1968,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
|||
|
||||
/* ADC CCR configuration */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
clrbits = ADC_CCR_DUAL_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DMACFG |
|
||||
ADC_CCR_MDMA_MASK | ADC_CCR_CKMODE_MASK | ADC_CCR_VREFEN |
|
||||
ADC_CCR_TSEN | ADC_CCR_VBATEN;
|
||||
|
|
@ -1993,12 +1979,10 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
|||
{
|
||||
stm32_modifyreg32(STM32_ADC12_CCR, clrbits, setbits);
|
||||
}
|
||||
#ifndef CONFIG_STM32_STM32F33XX
|
||||
else
|
||||
{
|
||||
stm32_modifyreg32(STM32_ADC34_CCR, clrbits, setbits);
|
||||
}
|
||||
#endif
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F4XXX) || \
|
||||
defined(CONFIG_STM32_STM32L15XX)
|
||||
|
|
@ -2066,7 +2050,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
|||
|
||||
leave_critical_section(flags);
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
ainfo("ISR: 0x%08x CR: 0x%08x CFGR: 0x%08x\n",
|
||||
adc_getreg(priv, STM32_ADC_ISR_OFFSET),
|
||||
adc_getreg(priv, STM32_ADC_CR_OFFSET),
|
||||
|
|
@ -2083,7 +2067,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
|||
adc_getreg(priv, STM32_ADC_SQR2_OFFSET),
|
||||
adc_getreg(priv, STM32_ADC_SQR3_OFFSET));
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
ainfo("SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET));
|
||||
#elif defined(CONFIG_STM32_STM32L15XX)
|
||||
ainfo("SQR4: 0x%08x SQR5: 0x%08x\n",
|
||||
|
|
@ -2091,17 +2075,15 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
|||
adc_getreg(priv, STM32_ADC_SQR5_OFFSET));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE)
|
||||
{
|
||||
ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC12_CCR));
|
||||
}
|
||||
#ifndef CONFIG_STM32_STM32F33XX
|
||||
else
|
||||
{
|
||||
ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC34_CCR));
|
||||
}
|
||||
#endif
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F4XXX) || \
|
||||
defined(CONFIG_STM32_STM32L15XX)
|
||||
|
|
@ -3101,9 +3083,8 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
|
|||
}
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX ||
|
||||
* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX ||
|
||||
* CONFIG_STM32_STM32F47XX || CONFIG_STM32_STM32F4XXX ||
|
||||
* CONFIG_STM32_STM32L15XX
|
||||
* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F47XX ||
|
||||
* CONFIG_STM32_STM32F4XXX || CONFIG_STM32_STM32L15XX
|
||||
*/
|
||||
#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 ||
|
||||
* CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4
|
||||
|
|
|
|||
|
|
@ -376,6 +376,13 @@
|
|||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || defined(CONFIG_STM32_HRTIM_ADC1_TRG2) || \
|
||||
defined(CONFIG_STM32_HRTIM_ADC3_TRG3) || defined(CONFIG_STM32_HRTIM_ADC4_TRG4)
|
||||
# define ADC1_HAVE_HRTIM
|
||||
#else
|
||||
# undef ADC1_HAVE_HRTIM
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM1_BASE
|
||||
|
|
@ -422,6 +429,13 @@
|
|||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_HRTIM_ADC2_TRG1) || defined(CONFIG_STM32_HRTIM_ADC2_TRG2) || \
|
||||
defined(CONFIG_STM32_HRTIM_ADC2_TRG3) || defined(CONFIG_STM32_HRTIM_ADC2_TRG4)
|
||||
# define ADC2_HAVE_HRTIM
|
||||
#else
|
||||
# undef ADC2_HAVE_HRTIM
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32_TIM1_BASE
|
||||
|
|
@ -532,6 +546,12 @@
|
|||
# undef ADC_HAVE_TIMER
|
||||
#endif
|
||||
|
||||
#if defined(ADC1_HAVE_HRTIM) || defined(ADC2_HAVE_HRTIM)
|
||||
# define ADC_HAVE_HRTIM
|
||||
#else
|
||||
# undef ADC_HAVE_HRTIM
|
||||
#endif
|
||||
|
||||
/* NOTE: The following assumes that all possible combinations of timers and
|
||||
* values are support EXTSEL. That is not so and it varies from one STM32
|
||||
* to another. But this (wrong) assumptions keeps the logic as simple as
|
||||
|
|
@ -543,7 +563,7 @@
|
|||
* for other 3 ADC's
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F30XX
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
# define ADC1_EXTSEL_T1CC1 ADC12_CFGR_EXTSEL_T1CC1
|
||||
# define ADC1_EXTSEL_T1CC2 ADC12_CFGR_EXTSEL_T1CC2
|
||||
# define ADC1_EXTSEL_T1CC3 ADC12_CFGR_EXTSEL_T1CC3
|
||||
|
|
@ -784,6 +804,10 @@
|
|||
# define ADC4_EXTSEL_T20CC3 ADC34_CFGR_EXTSEL_T20CC3
|
||||
# define ADC4_EXTSEL_T20CC4 ADC34_CFGR_EXTSEL_T20CC4
|
||||
# define ADC4_EXTSEL_T20TRGO ADC34_CFGR_EXTSEL_T20TRGO
|
||||
# define ADC1_EXTSEL_HRTTRG1 ADC12_CFGR_EXTSEL_HRT1TRG1
|
||||
# define ADC1_EXTSEL_HRTTRG3 ADC12_CFGR_EXTSEL_HRT1TRG3
|
||||
# define ADC2_EXTSEL_HRTTRG1 ADC12_CFGR_EXTSEL_HRT1TRG1
|
||||
# define ADC2_EXTSEL_HRTTRG3 ADC12_CFGR_EXTSEL_HRT1TRG3
|
||||
#else
|
||||
# define ADC1_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
|
||||
# define ADC1_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
|
||||
|
|
@ -1027,6 +1051,257 @@
|
|||
# define ADC4_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO
|
||||
#endif
|
||||
|
||||
/* JEXTSEL definitions.
|
||||
* NOTE: Assumptions like for EXTSEL definitions (look above)
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
# define ADC1_JEXTSEL_T1CC1 ADC12_CFGR_JEXTSEL_T1CC1
|
||||
# define ADC1_JEXTSEL_T1CC2 ADC12_CFGR_JEXTSEL_T1CC2
|
||||
# define ADC1_JEXTSEL_T1CC3 ADC12_CFGR_JEXTSEL_T1CC3
|
||||
# define ADC1_JEXTSEL_T1CC4 ADC12_CFGR_JEXTSEL_T1CC4
|
||||
# define ADC1_JEXTSEL_T1TRGO ADC12_CFGR_JEXTSEL_T1TRGO
|
||||
# define ADC2_JEXTSEL_T1CC1 ADC12_CFGR_JEXTSEL_T1CC1
|
||||
# define ADC2_JEXTSEL_T1CC2 ADC12_CFGR_JEXTSEL_T1CC2
|
||||
# define ADC2_JEXTSEL_T1CC3 ADC12_CFGR_JEXTSEL_T1CC3
|
||||
# define ADC2_JEXTSEL_T1CC4 ADC12_CFGR_JEXTSEL_T1CC4
|
||||
# define ADC2_JEXTSEL_T1TRGO ADC12_CFGR_JEXTSEL_T1TRGO
|
||||
# define ADC3_JEXTSEL_T1CC1 ADC34_CFGR_JEXTSEL_T1CC1
|
||||
# define ADC3_JEXTSEL_T1CC2 ADC34_CFGR_JEXTSEL_T1CC2
|
||||
# define ADC3_JEXTSEL_T1CC3 ADC34_CFGR_JEXTSEL_T1CC3
|
||||
# define ADC3_JEXTSEL_T1CC4 ADC34_CFGR_JEXTSEL_T1CC4
|
||||
# define ADC3_JEXTSEL_T1TRGO ADC34_CFGR_JEXTSEL_T1TRGO
|
||||
# define ADC4_JEXTSEL_T1CC1 ADC34_CFGR_JEXTSEL_T1CC1
|
||||
# define ADC4_JEXTSEL_T1CC2 ADC34_CFGR_JEXTSEL_T1CC2
|
||||
# define ADC4_JEXTSEL_T1CC3 ADC34_CFGR_JEXTSEL_T1CC3
|
||||
# define ADC4_JEXTSEL_T1CC4 ADC34_CFGR_JEXTSEL_T1CC4
|
||||
# define ADC4_JEXTSEL_T1TRGO ADC34_CFGR_JEXTSEL_T1TRGO
|
||||
# define ADC1_JEXTSEL_T2CC1 ADC12_CFGR_JEXTSEL_T2CC1
|
||||
# define ADC1_JEXTSEL_T2CC2 ADC12_CFGR_JEXTSEL_T2CC2
|
||||
# define ADC1_JEXTSEL_T2CC3 ADC12_CFGR_JEXTSEL_T2CC3
|
||||
# define ADC1_JEXTSEL_T2CC4 ADC12_CFGR_JEXTSEL_T2CC4
|
||||
# define ADC1_JEXTSEL_T2TRGO ADC12_CFGR_JEXTSEL_T2TRGO
|
||||
# define ADC2_JEXTSEL_T2CC1 ADC12_CFGR_JEXTSEL_T2CC1
|
||||
# define ADC2_JEXTSEL_T2CC2 ADC12_CFGR_JEXTSEL_T2CC2
|
||||
# define ADC2_JEXTSEL_T2CC3 ADC12_CFGR_JEXTSEL_T2CC3
|
||||
# define ADC2_JEXTSEL_T2CC4 ADC12_CFGR_JEXTSEL_T2CC4
|
||||
# define ADC2_JEXTSEL_T2TRGO ADC12_CFGR_JEXTSEL_T2TRGO
|
||||
# define ADC3_JEXTSEL_T2CC1 ADC34_CFGR_JEXTSEL_T2CC1
|
||||
# define ADC3_JEXTSEL_T2CC2 ADC34_CFGR_JEXTSEL_T2CC2
|
||||
# define ADC3_JEXTSEL_T2CC3 ADC34_CFGR_JEXTSEL_T2CC3
|
||||
# define ADC3_JEXTSEL_T2CC4 ADC34_CFGR_JEXTSEL_T2CC4
|
||||
# define ADC3_JEXTSEL_T2TRGO ADC34_CFGR_JEXTSEL_T2TRGO
|
||||
# define ADC4_JEXTSEL_T2CC1 ADC34_CFGR_JEXTSEL_T2CC1
|
||||
# define ADC4_JEXTSEL_T2CC2 ADC34_CFGR_JEXTSEL_T2CC2
|
||||
# define ADC4_JEXTSEL_T2CC3 ADC34_CFGR_JEXTSEL_T2CC3
|
||||
# define ADC4_JEXTSEL_T2CC4 ADC34_CFGR_JEXTSEL_T2CC4
|
||||
# define ADC4_JEXTSEL_T2TRGO ADC34_CFGR_JEXTSEL_T2TRGO
|
||||
# define ADC1_JEXTSEL_T3CC1 ADC12_CFGR_JEXTSEL_T3CC1
|
||||
# define ADC1_JEXTSEL_T3CC2 ADC12_CFGR_JEXTSEL_T3CC2
|
||||
# define ADC1_JEXTSEL_T3CC3 ADC12_CFGR_JEXTSEL_T3CC3
|
||||
# define ADC1_JEXTSEL_T3CC4 ADC12_CFGR_JEXTSEL_T3CC4
|
||||
# define ADC1_JEXTSEL_T3TRGO ADC12_CFGR_JEXTSEL_T3TRGO
|
||||
# define ADC2_JEXTSEL_T3CC1 ADC12_CFGR_JEXTSEL_T3CC1
|
||||
# define ADC2_JEXTSEL_T3CC2 ADC12_CFGR_JEXTSEL_T3CC2
|
||||
# define ADC2_JEXTSEL_T3CC3 ADC12_CFGR_JEXTSEL_T3CC3
|
||||
# define ADC2_JEXTSEL_T3CC4 ADC12_CFGR_JEXTSEL_T3CC4
|
||||
# define ADC2_JEXTSEL_T3TRGO ADC12_CFGR_JEXTSEL_T3TRGO
|
||||
# define ADC3_JEXTSEL_T3CC1 ADC34_CFGR_JEXTSEL_T3CC1
|
||||
# define ADC3_JEXTSEL_T3CC2 ADC34_CFGR_JEXTSEL_T3CC2
|
||||
# define ADC3_JEXTSEL_T3CC3 ADC34_CFGR_JEXTSEL_T3CC3
|
||||
# define ADC3_JEXTSEL_T3CC4 ADC34_CFGR_JEXTSEL_T3CC4
|
||||
# define ADC3_JEXTSEL_T3TRGO ADC34_CFGR_JEXTSEL_T3TRGO
|
||||
# define ADC4_JEXTSEL_T3CC1 ADC34_CFGR_JEXTSEL_T3CC1
|
||||
# define ADC4_JEXTSEL_T3CC2 ADC34_CFGR_JEXTSEL_T3CC2
|
||||
# define ADC4_JEXTSEL_T3CC3 ADC34_CFGR_JEXTSEL_T3CC3
|
||||
# define ADC4_JEXTSEL_T3CC4 ADC34_CFGR_JEXTSEL_T3CC4
|
||||
# define ADC4_JEXTSEL_T3TRGO ADC34_CFGR_JEXTSEL_T3TRGO
|
||||
# define ADC1_JEXTSEL_T4CC1 ADC12_CFGR_JEXTSEL_T4CC1
|
||||
# define ADC1_JEXTSEL_T4CC2 ADC12_CFGR_JEXTSEL_T4CC2
|
||||
# define ADC1_JEXTSEL_T4CC3 ADC12_CFGR_JEXTSEL_T4CC3
|
||||
# define ADC1_JEXTSEL_T4CC4 ADC12_CFGR_JEXTSEL_T4CC4
|
||||
# define ADC1_JEXTSEL_T4TRGO ADC12_CFGR_JEXTSEL_T4TRGO
|
||||
# define ADC2_JEXTSEL_T4CC1 ADC12_CFGR_JEXTSEL_T4CC1
|
||||
# define ADC2_JEXTSEL_T4CC2 ADC12_CFGR_JEXTSEL_T4CC2
|
||||
# define ADC2_JEXTSEL_T4CC3 ADC12_CFGR_JEXTSEL_T4CC3
|
||||
# define ADC2_JEXTSEL_T4CC4 ADC12_CFGR_JEXTSEL_T4CC4
|
||||
# define ADC2_JEXTSEL_T4TRGO ADC12_CFGR_JEXTSEL_T4TRGO
|
||||
# define ADC3_JEXTSEL_T4CC1 ADC34_CFGR_JEXTSEL_T4CC1
|
||||
# define ADC3_JEXTSEL_T4CC2 ADC34_CFGR_JEXTSEL_T4CC2
|
||||
# define ADC3_JEXTSEL_T4CC3 ADC34_CFGR_JEXTSEL_T4CC3
|
||||
# define ADC3_JEXTSEL_T4CC4 ADC34_CFGR_JEXTSEL_T4CC4
|
||||
# define ADC3_JEXTSEL_T4TRGO ADC34_CFGR_JEXTSEL_T4TRGO
|
||||
# define ADC4_JEXTSEL_T4CC1 ADC34_CFGR_JEXTSEL_T4CC1
|
||||
# define ADC4_JEXTSEL_T4CC2 ADC34_CFGR_JEXTSEL_T4CC2
|
||||
# define ADC4_JEXTSEL_T4CC3 ADC34_CFGR_JEXTSEL_T4CC3
|
||||
# define ADC4_JEXTSEL_T4CC4 ADC34_CFGR_JEXTSEL_T4CC4
|
||||
# define ADC4_JEXTSEL_T4TRGO ADC34_CFGR_JEXTSEL_T4TRGO
|
||||
# define ADC1_JEXTSEL_T5CC1 ADC12_CFGR_JEXTSEL_T5CC1
|
||||
# define ADC1_JEXTSEL_T5CC2 ADC12_CFGR_JEXTSEL_T5CC2
|
||||
# define ADC1_JEXTSEL_T5CC3 ADC12_CFGR_JEXTSEL_T5CC3
|
||||
# define ADC1_JEXTSEL_T5CC4 ADC12_CFGR_JEXTSEL_T5CC4
|
||||
# define ADC1_JEXTSEL_T5TRGO ADC12_CFGR_JEXTSEL_T5TRGO
|
||||
# define ADC2_JEXTSEL_T5CC1 ADC12_CFGR_JEXTSEL_T5CC1
|
||||
# define ADC2_JEXTSEL_T5CC2 ADC12_CFGR_JEXTSEL_T5CC2
|
||||
# define ADC2_JEXTSEL_T5CC3 ADC12_CFGR_JEXTSEL_T5CC3
|
||||
# define ADC2_JEXTSEL_T5CC4 ADC12_CFGR_JEXTSEL_T5CC4
|
||||
# define ADC2_JEXTSEL_T5TRGO ADC12_CFGR_JEXTSEL_T5TRGO
|
||||
# define ADC3_JEXTSEL_T5CC1 ADC34_CFGR_JEXTSEL_T5CC1
|
||||
# define ADC3_JEXTSEL_T5CC2 ADC34_CFGR_JEXTSEL_T5CC2
|
||||
# define ADC3_JEXTSEL_T5CC3 ADC34_CFGR_JEXTSEL_T5CC3
|
||||
# define ADC3_JEXTSEL_T5CC4 ADC34_CFGR_JEXTSEL_T5CC4
|
||||
# define ADC3_JEXTSEL_T5TRGO ADC34_CFGR_JEXTSEL_T5TRGO
|
||||
# define ADC4_JEXTSEL_T5CC1 ADC34_CFGR_JEXTSEL_T5CC1
|
||||
# define ADC4_JEXTSEL_T5CC2 ADC34_CFGR_JEXTSEL_T5CC2
|
||||
# define ADC4_JEXTSEL_T5CC3 ADC34_CFGR_JEXTSEL_T5CC3
|
||||
# define ADC4_JEXTSEL_T5CC4 ADC34_CFGR_JEXTSEL_T5CC4
|
||||
# define ADC4_JEXTSEL_T5TRGO ADC34_CFGR_JEXTSEL_T5TRGO
|
||||
# define ADC1_JEXTSEL_T6CC1 ADC12_CFGR_JEXTSEL_T6CC1
|
||||
# define ADC1_JEXTSEL_T6CC2 ADC12_CFGR_JEXTSEL_T6CC2
|
||||
# define ADC1_JEXTSEL_T6CC3 ADC12_CFGR_JEXTSEL_T6CC3
|
||||
# define ADC1_JEXTSEL_T6CC4 ADC12_CFGR_JEXTSEL_T6CC4
|
||||
# define ADC1_JEXTSEL_T6TRGO ADC12_CFGR_JEXTSEL_T6TRGO
|
||||
# define ADC2_JEXTSEL_T6CC1 ADC12_CFGR_JEXTSEL_T6CC1
|
||||
# define ADC2_JEXTSEL_T6CC2 ADC12_CFGR_JEXTSEL_T6CC2
|
||||
# define ADC2_JEXTSEL_T6CC3 ADC12_CFGR_JEXTSEL_T6CC3
|
||||
# define ADC2_JEXTSEL_T6CC4 ADC12_CFGR_JEXTSEL_T6CC4
|
||||
# define ADC2_JEXTSEL_T6TRGO ADC12_CFGR_JEXTSEL_T6TRGO
|
||||
# define ADC3_JEXTSEL_T6CC1 ADC34_CFGR_JEXTSEL_T6CC1
|
||||
# define ADC3_JEXTSEL_T6CC2 ADC34_CFGR_JEXTSEL_T6CC2
|
||||
# define ADC3_JEXTSEL_T6CC3 ADC34_CFGR_JEXTSEL_T6CC3
|
||||
# define ADC3_JEXTSEL_T6CC4 ADC34_CFGR_JEXTSEL_T6CC4
|
||||
# define ADC3_JEXTSEL_T6TRGO ADC34_CFGR_JEXTSEL_T6TRGO
|
||||
# define ADC4_JEXTSEL_T6CC1 ADC34_CFGR_JEXTSEL_T6CC1
|
||||
# define ADC4_JEXTSEL_T6CC2 ADC34_CFGR_JEXTSEL_T6CC2
|
||||
# define ADC4_JEXTSEL_T6CC3 ADC34_CFGR_JEXTSEL_T6CC3
|
||||
# define ADC4_JEXTSEL_T6CC4 ADC34_CFGR_JEXTSEL_T6CC4
|
||||
# define ADC4_JEXTSEL_T6TRGO ADC34_CFGR_JEXTSEL_T6TRGO
|
||||
# define ADC1_JEXTSEL_T7CC1 ADC12_CFGR_JEXTSEL_T7CC1
|
||||
# define ADC1_JEXTSEL_T7CC2 ADC12_CFGR_JEXTSEL_T7CC2
|
||||
# define ADC1_JEXTSEL_T7CC3 ADC12_CFGR_JEXTSEL_T7CC3
|
||||
# define ADC1_JEXTSEL_T7CC4 ADC12_CFGR_JEXTSEL_T7CC4
|
||||
# define ADC1_JEXTSEL_T7TRGO ADC12_CFGR_JEXTSEL_T7TRGO
|
||||
# define ADC2_JEXTSEL_T7CC1 ADC12_CFGR_JEXTSEL_T7CC1
|
||||
# define ADC2_JEXTSEL_T7CC2 ADC12_CFGR_JEXTSEL_T7CC2
|
||||
# define ADC2_JEXTSEL_T7CC3 ADC12_CFGR_JEXTSEL_T7CC3
|
||||
# define ADC2_JEXTSEL_T7CC4 ADC12_CFGR_JEXTSEL_T7CC4
|
||||
# define ADC2_JEXTSEL_T7TRGO ADC12_CFGR_JEXTSEL_T7TRGO
|
||||
# define ADC3_JEXTSEL_T7CC1 ADC34_CFGR_JEXTSEL_T7CC1
|
||||
# define ADC3_JEXTSEL_T7CC2 ADC34_CFGR_JEXTSEL_T7CC2
|
||||
# define ADC3_JEXTSEL_T7CC3 ADC34_CFGR_JEXTSEL_T7CC3
|
||||
# define ADC3_JEXTSEL_T7CC4 ADC34_CFGR_JEXTSEL_T7CC4
|
||||
# define ADC3_JEXTSEL_T7TRGO ADC34_CFGR_JEXTSEL_T7TRGO
|
||||
# define ADC4_JEXTSEL_T7CC1 ADC34_CFGR_JEXTSEL_T7CC1
|
||||
# define ADC4_JEXTSEL_T7CC2 ADC34_CFGR_JEXTSEL_T7CC2
|
||||
# define ADC4_JEXTSEL_T7CC3 ADC34_CFGR_JEXTSEL_T7CC3
|
||||
# define ADC4_JEXTSEL_T7CC4 ADC34_CFGR_JEXTSEL_T7CC4
|
||||
# define ADC4_JEXTSEL_T7TRGO ADC34_CFGR_JEXTSEL_T7TRGO
|
||||
# define ADC1_JEXTSEL_T8CC1 ADC12_CFGR_JEXTSEL_T8CC1
|
||||
# define ADC1_JEXTSEL_T8CC2 ADC12_CFGR_JEXTSEL_T8CC2
|
||||
# define ADC1_JEXTSEL_T8CC3 ADC12_CFGR_JEXTSEL_T8CC3
|
||||
# define ADC1_JEXTSEL_T8CC4 ADC12_CFGR_JEXTSEL_T8CC4
|
||||
# define ADC1_JEXTSEL_T8TRGO ADC12_CFGR_JEXTSEL_T8TRGO
|
||||
# define ADC2_JEXTSEL_T8CC1 ADC12_CFGR_JEXTSEL_T8CC1
|
||||
# define ADC2_JEXTSEL_T8CC2 ADC12_CFGR_JEXTSEL_T8CC2
|
||||
# define ADC2_JEXTSEL_T8CC3 ADC12_CFGR_JEXTSEL_T8CC3
|
||||
# define ADC2_JEXTSEL_T8CC4 ADC12_CFGR_JEXTSEL_T8CC4
|
||||
# define ADC2_JEXTSEL_T8TRGO ADC12_CFGR_JEXTSEL_T8TRGO
|
||||
# define ADC3_JEXTSEL_T8CC1 ADC34_CFGR_JEXTSEL_T8CC1
|
||||
# define ADC3_JEXTSEL_T8CC2 ADC34_CFGR_JEXTSEL_T8CC2
|
||||
# define ADC3_JEXTSEL_T8CC3 ADC34_CFGR_JEXTSEL_T8CC3
|
||||
# define ADC3_JEXTSEL_T8CC4 ADC34_CFGR_JEXTSEL_T8CC4
|
||||
# define ADC3_JEXTSEL_T8TRGO ADC34_CFGR_JEXTSEL_T8TRGO
|
||||
# define ADC4_JEXTSEL_T8CC1 ADC34_CFGR_JEXTSEL_T8CC1
|
||||
# define ADC4_JEXTSEL_T8CC2 ADC34_CFGR_JEXTSEL_T8CC2
|
||||
# define ADC4_JEXTSEL_T8CC3 ADC34_CFGR_JEXTSEL_T8CC3
|
||||
# define ADC4_JEXTSEL_T8CC4 ADC34_CFGR_JEXTSEL_T8CC4
|
||||
# define ADC4_JEXTSEL_T8TRGO ADC34_CFGR_JEXTSEL_T8TRGO
|
||||
# define ADC1_JEXTSEL_T9CC1 ADC12_CFGR_JEXTSEL_T9CC1
|
||||
# define ADC1_JEXTSEL_T9CC2 ADC12_CFGR_JEXTSEL_T9CC2
|
||||
# define ADC1_JEXTSEL_T9CC3 ADC12_CFGR_JEXTSEL_T9CC3
|
||||
# define ADC1_JEXTSEL_T9CC4 ADC12_CFGR_JEXTSEL_T9CC4
|
||||
# define ADC1_JEXTSEL_T9TRGO ADC12_CFGR_JEXTSEL_T9TRGO
|
||||
# define ADC2_JEXTSEL_T9CC1 ADC12_CFGR_JEXTSEL_T9CC1
|
||||
# define ADC2_JEXTSEL_T9CC2 ADC12_CFGR_JEXTSEL_T9CC2
|
||||
# define ADC2_JEXTSEL_T9CC3 ADC12_CFGR_JEXTSEL_T9CC3
|
||||
# define ADC2_JEXTSEL_T9CC4 ADC12_CFGR_JEXTSEL_T9CC4
|
||||
# define ADC2_JEXTSEL_T9TRGO ADC12_CFGR_JEXTSEL_T9TRGO
|
||||
# define ADC3_JEXTSEL_T9CC1 ADC34_CFGR_JEXTSEL_T9CC1
|
||||
# define ADC3_JEXTSEL_T9CC2 ADC34_CFGR_JEXTSEL_T9CC2
|
||||
# define ADC3_JEXTSEL_T9CC3 ADC34_CFGR_JEXTSEL_T9CC3
|
||||
# define ADC3_JEXTSEL_T9CC4 ADC34_CFGR_JEXTSEL_T9CC4
|
||||
# define ADC3_JEXTSEL_T9TRGO ADC34_CFGR_JEXTSEL_T9TRGO
|
||||
# define ADC4_JEXTSEL_T9CC1 ADC34_CFGR_JEXTSEL_T9CC1
|
||||
# define ADC4_JEXTSEL_T9CC2 ADC34_CFGR_JEXTSEL_T9CC2
|
||||
# define ADC4_JEXTSEL_T9CC3 ADC34_CFGR_JEXTSEL_T9CC3
|
||||
# define ADC4_JEXTSEL_T9CC4 ADC34_CFGR_JEXTSEL_T9CC4
|
||||
# define ADC4_JEXTSEL_T9TRGO ADC34_CFGR_JEXTSEL_T9TRGO
|
||||
# define ADC1_JEXTSEL_T10CC1 ADC12_CFGR_JEXTSEL_T10CC1
|
||||
# define ADC1_JEXTSEL_T10CC2 ADC12_CFGR_JEXTSEL_T10CC2
|
||||
# define ADC1_JEXTSEL_T10CC3 ADC12_CFGR_JEXTSEL_T10CC3
|
||||
# define ADC1_JEXTSEL_T10CC4 ADC12_CFGR_JEXTSEL_T10CC4
|
||||
# define ADC1_JEXTSEL_T10TRGO ADC12_CFGR_JEXTSEL_T10TRGO
|
||||
# define ADC2_JEXTSEL_T10CC1 ADC12_CFGR_JEXTSEL_T10CC1
|
||||
# define ADC2_JEXTSEL_T10CC2 ADC12_CFGR_JEXTSEL_T10CC2
|
||||
# define ADC2_JEXTSEL_T10CC3 ADC12_CFGR_JEXTSEL_T10CC3
|
||||
# define ADC2_JEXTSEL_T10CC4 ADC12_CFGR_JEXTSEL_T10CC4
|
||||
# define ADC2_JEXTSEL_T10TRGO ADC12_CFGR_JEXTSEL_T10TRGO
|
||||
# define ADC3_JEXTSEL_T10CC1 ADC34_CFGR_JEXTSEL_T10CC1
|
||||
# define ADC3_JEXTSEL_T10CC2 ADC34_CFGR_JEXTSEL_T10CC2
|
||||
# define ADC3_JEXTSEL_T10CC3 ADC34_CFGR_JEXTSEL_T10CC3
|
||||
# define ADC3_JEXTSEL_T10CC4 ADC34_CFGR_JEXTSEL_T10CC4
|
||||
# define ADC3_JEXTSEL_T10TRGO ADC34_CFGR_JEXTSEL_T10TRGO
|
||||
# define ADC4_JEXTSEL_T10CC1 ADC34_CFGR_JEXTSEL_T10CC1
|
||||
# define ADC4_JEXTSEL_T10CC2 ADC34_CFGR_JEXTSEL_T10CC2
|
||||
# define ADC4_JEXTSEL_T10CC3 ADC34_CFGR_JEXTSEL_T10CC3
|
||||
# define ADC4_JEXTSEL_T10CC4 ADC34_CFGR_JEXTSEL_T10CC4
|
||||
# define ADC4_JEXTSEL_T10TRGO ADC34_CFGR_JEXTSEL_T10TRGO
|
||||
# define ADC1_JEXTSEL_T15CC1 ADC12_CFGR_JEXTSEL_T15CC1
|
||||
# define ADC1_JEXTSEL_T15CC2 ADC12_CFGR_JEXTSEL_T15CC2
|
||||
# define ADC1_JEXTSEL_T15CC3 ADC12_CFGR_JEXTSEL_T15CC3
|
||||
# define ADC1_JEXTSEL_T15CC4 ADC12_CFGR_JEXTSEL_T15CC4
|
||||
# define ADC1_JEXTSEL_T15TRGO ADC12_CFGR_JEXTSEL_T15TRGO
|
||||
# define ADC2_JEXTSEL_T15CC1 ADC12_CFGR_JEXTSEL_T15CC1
|
||||
# define ADC2_JEXTSEL_T15CC2 ADC12_CFGR_JEXTSEL_T15CC2
|
||||
# define ADC2_JEXTSEL_T15CC3 ADC12_CFGR_JEXTSEL_T15CC3
|
||||
# define ADC2_JEXTSEL_T15CC4 ADC12_CFGR_JEXTSEL_T15CC4
|
||||
# define ADC2_JEXTSEL_T15TRGO ADC12_CFGR_JEXTSEL_T15TRGO
|
||||
# define ADC3_JEXTSEL_T15CC1 ADC34_CFGR_JEXTSEL_T15CC1
|
||||
# define ADC3_JEXTSEL_T15CC2 ADC34_CFGR_JEXTSEL_T15CC2
|
||||
# define ADC3_JEXTSEL_T15CC3 ADC34_CFGR_JEXTSEL_T15CC3
|
||||
# define ADC3_JEXTSEL_T15CC4 ADC34_CFGR_JEXTSEL_T15CC4
|
||||
# define ADC3_JEXTSEL_T15TRGO ADC34_CFGR_JEXTSEL_T15TRGO
|
||||
# define ADC4_JEXTSEL_T15CC1 ADC34_CFGR_JEXTSEL_T15CC1
|
||||
# define ADC4_JEXTSEL_T15CC2 ADC34_CFGR_JEXTSEL_T15CC2
|
||||
# define ADC4_JEXTSEL_T15CC3 ADC34_CFGR_JEXTSEL_T15CC3
|
||||
# define ADC4_JEXTSEL_T15CC4 ADC34_CFGR_JEXTSEL_T15CC4
|
||||
# define ADC4_JEXTSEL_T15TRGO ADC34_CFGR_JEXTSEL_T15TRGO
|
||||
# define ADC1_JEXTSEL_T20CC1 ADC12_CFGR_JEXTSEL_T20CC1
|
||||
# define ADC1_JEXTSEL_T20CC2 ADC12_CFGR_JEXTSEL_T20CC2
|
||||
# define ADC1_JEXTSEL_T20CC3 ADC12_CFGR_JEXTSEL_T20CC3
|
||||
# define ADC1_JEXTSEL_T20CC4 ADC12_CFGR_JEXTSEL_T20CC4
|
||||
# define ADC1_JEXTSEL_T20TRGO ADC12_CFGR_JEXTSEL_T20TRGO
|
||||
# define ADC2_JEXTSEL_T20CC1 ADC12_CFGR_JEXTSEL_T20CC1
|
||||
# define ADC2_JEXTSEL_T20CC2 ADC12_CFGR_JEXTSEL_T20CC2
|
||||
# define ADC2_JEXTSEL_T20CC3 ADC12_CFGR_JEXTSEL_T20CC3
|
||||
# define ADC2_JEXTSEL_T20CC4 ADC12_CFGR_JEXTSEL_T20CC4
|
||||
# define ADC2_JEXTSEL_T20TRGO ADC12_CFGR_JEXTSEL_T20TRGO
|
||||
# define ADC3_JEXTSEL_T20CC1 ADC34_CFGR_JEXTSEL_T20CC1
|
||||
# define ADC3_JEXTSEL_T20CC2 ADC34_CFGR_JEXTSEL_T20CC2
|
||||
# define ADC3_JEXTSEL_T20CC3 ADC34_CFGR_JEXTSEL_T20CC3
|
||||
# define ADC3_JEXTSEL_T20CC4 ADC34_CFGR_JEXTSEL_T20CC4
|
||||
# define ADC3_JEXTSEL_T20TRGO ADC34_CFGR_JEXTSEL_T20TRGO
|
||||
# define ADC4_JEXTSEL_T20CC1 ADC34_CFGR_JEXTSEL_T20CC1
|
||||
# define ADC4_JEXTSEL_T20CC2 ADC34_CFGR_JEXTSEL_T20CC2
|
||||
# define ADC4_JEXTSEL_T20CC3 ADC34_CFGR_JEXTSEL_T20CC3
|
||||
# define ADC4_JEXTSEL_T20CC4 ADC34_CFGR_JEXTSEL_T20CC4
|
||||
# define ADC4_JEXTSEL_T20TRGO ADC34_CFGR_JEXTSEL_T20TRGO
|
||||
# define ADC1_JEXTSEL_HRTTRG2 ADC12_CFGR_JEXTSEL_HRT1TRG2
|
||||
# define ADC1_JEXTSEL_HRTTRG4 ADC12_CFGR_JEXTSEL_HRT1TRG4
|
||||
# define ADC2_JEXTSEL_HRTTRG2 ADC12_CFGR_JEXTSEL_HRT1TRG2
|
||||
# define ADC2_JEXTSEL_HRTTRG4 ADC12_CFGR_JEXTSEL_HRT1TRG4
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_ADC1)
|
||||
# if CONFIG_STM32_ADC1_TIMTRIG == 0
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1
|
||||
|
|
@ -1181,6 +1456,18 @@
|
|||
# else
|
||||
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_HRTIM_ADC1_TRG1)
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_HRTTRG1
|
||||
#elif defined(CONFIG_STM32_HRTIM_ADC1_TRG3)
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_HRTTRG3
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_HRTIM_ADC1_TRG2)
|
||||
# define ADC1_JEXTSEL_VALUE ADC1_JEXTSEL_HRTTRG2
|
||||
#elif defined(CONFIG_STM32_HRTIM_ADC1_TRG3)
|
||||
# define ADC1_JEXTSEL_VALUE ADC1_JEXTSEL_HRTTRG4
|
||||
#else
|
||||
# define ADC1_JEXTSEL_VALUE 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_ADC2)
|
||||
|
|
@ -1295,6 +1582,18 @@
|
|||
# else
|
||||
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_HRTIM_ADC2_TRG1)
|
||||
# define ADC2_EXTSEL_VALUE ADC1_EXTSEL_HRTTRG1
|
||||
#elif defined(CONFIG_STM32_HRTIM_ADC1_TRG3)
|
||||
# define ADC2_EXTSEL_VALUE ADC1_EXTSEL_HRTTRG3
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_HRTIM_ADC2_TRG2)
|
||||
# define ADC2_JEXTSEL_VALUE ADC2_JEXTSEL_HRTTRG2
|
||||
#elif defined(CONFIG_STM32_HRTIM_ADC2_TRG3)
|
||||
# define ADC2_JEXTSEL_VALUE ADC2_JEXTSEL_HRTTRG4
|
||||
#else
|
||||
# define ADC2_JEXTSEL_VALUE 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_ADC3)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue