risc-v: Let g_cpu_basestack determined at compile time

Fix the CPU1 idle tasks stack corruption since the cpux's idle stack
is loaded from g_cpu_basestack (data section) before, but on this time
it maybe not ready since it is initialized by CPU0, and the value
from g_cpu_basestack is random.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>

arch/risc-v/src/common/riscv_cpuidlestack.c

@@ -83,7 +83,7 @@ static uint8_t aligned_data(16) cpu7_idlestack[CONFIG_IDLETHREAD_STACKSIZE];
  * Public Data
  ****************************************************************************/
 
-uint8_t *g_cpu_basestack[CONFIG_SMP_NCPUS] =
+const uint8_t * const g_cpu_basestack[CONFIG_SMP_NCPUS] =
 {
     (uint8_t *)&_ebss,
 #if CONFIG_SMP_NCPUS > 1

arch/risc-v/src/common/riscv_internal.h

@@ -117,7 +117,7 @@ EXTERN uintptr_t g_idle_topstack;
 
 /* Address of per-cpu idle stack base */
 
-EXTERN uint8_t *g_cpu_basestack[CONFIG_SMP_NCPUS];
+EXTERN const uint8_t * const g_cpu_basestack[CONFIG_SMP_NCPUS];
 
 /* Address of the saved user stack pointer */