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In ARMV71-Xplained clock configuration, divider was set to 25 to get 25*12MHz=300MHz CPU clock. The correct multiplier is 24 becaue the calculatin if (24+1)*12MHz. So the board was running at 312MHz. From Efim Monjak.

This commit is contained in:
Efim Monjak 2015-06-26 06:52:37 -06:00 committed by Gregory Nutt
parent ce7955bae8
commit 5a4bb1714d
1 changed files with 1 additions and 3 deletions
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4
configs/samv71-xult/include/board.h
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@ -82,13 +82,11 @@
* Yields:
*
* PLLACK = 25 * 12MHz / 1 = 300MHz
*
* REVISIT: Isn't the actual multiplier = MUL+1? Is this being overclocked at 312MHz?
*/
#define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST
#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
#define BOARD_CKGR_PLLAR_MUL PMC_CKGR_PLLAR_MUL(25)
#define BOARD_CKGR_PLLAR_MUL PMC_CKGR_PLLAR_MUL(24)
#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
/* PMC master clock register settings.