DK-TM4C129X: Fixes to get clean build. Logic is still not complete, however
This commit is contained in:
Gregory Nutt
parent
49a22f1ccb
commit
55a3c57399
|
|
@ -370,6 +370,7 @@
|
|||
# define NR_IRQS (155) /* (Really fewer because of reserved vectors) */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_TM4C129XNC)
|
||||
|
||||
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
|
||||
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
|
||||
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
|
||||
|
|
@ -437,8 +438,8 @@
|
|||
# define TIVA_IRQ_UART5 (74) /* Vector 74: UART 5 */
|
||||
# define TIVA_IRQ_UART6 (75) /* Vector 75: UART 6 */
|
||||
# define TIVA_IRQ_UART7 (76) /* Vector 76: UART 7 */
|
||||
# define TIVA_IRQ_I2C1 (77) /* Vector 77: I2C 2 */
|
||||
# define TIVA_IRQ_I2C1 (78) /* Vector 78: I2C 3 */
|
||||
# define TIVA_IRQ_I2C2 (77) /* Vector 77: I2C 2 */
|
||||
# define TIVA_IRQ_I2C3 (78) /* Vector 78: I2C 3 */
|
||||
# define TIVA_IRQ_TIMER4A (79) /* Vector 79: 16/32-Bit Timer 4 A */
|
||||
|
||||
# define TIVA_IRQ_TIMER4B (80) /* Vector 80: 16/32-Bit Timer 4 B */
|
||||
|
|
|
|||
|
|
@ -52,8 +52,26 @@
|
|||
defined(CONFIG_ARCH_CHIP_LM3S8962) || defined(CONFIG_ARCH_CHIP_LM3S9B96) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI) || \
|
||||
defined(CONFIG_ARCH_CHIP_CC3200)
|
||||
|
||||
/* These parts all support a 1KiB erase page size and a total FLASH memory size
|
||||
* of 256Kib or 256 pages.
|
||||
*/
|
||||
|
||||
# define TIVA_FLASH_NPAGES 256
|
||||
# define TIVA_FLASH_PAGESIZE 1024
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_TM4C129XNC)
|
||||
|
||||
/* For the TM4C129X family, the Flash memory is configured in groups of four banks
|
||||
* four banks of 16K x 128 bits (4 * 256 KB total) which are two-way interleaved.
|
||||
* Because the memory is two-way interleaved and each bank individually is an 8-KB
|
||||
* sector, when the user erases a sector, using the ERASE bits in the Flash Memory
|
||||
* Control (FMC) register, it is a 16 KB erase.
|
||||
*/
|
||||
|
||||
# define TIVA_FLASH_NPAGES 64
|
||||
# define TIVA_FLASH_PAGESIZE 16384
|
||||
|
||||
#else
|
||||
# warning "No flash dimensions defined for selected chip."
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@
|
|||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* REVISIT: Why do we not use the AHB aperture for all GPIO accesses? */
|
||||
|
||||
#define TIVA_GPIOK_BASE TIVA_GPIOKAHB_BASE
|
||||
#define TIVA_GPIOL_BASE TIVA_GPIOLAHB_BASE
|
||||
|
|
@ -53,6 +54,9 @@
|
|||
#define TIVA_GPION_BASE TIVA_GPIONAHB_BASE
|
||||
#define TIVA_GPIOP_BASE TIVA_GPIOPAHB_BASE
|
||||
#define TIVA_GPIOQ_BASE TIVA_GPIOQAHB_BASE
|
||||
#define TIVA_GPIOR_BASE TIVA_GPIORAHB_BASE
|
||||
#define TIVA_GPIOS_BASE TIVA_GPIOSAHB_BASE
|
||||
#define TIVA_GPIOT_BASE TIVA_GPIOTAHB_BASE
|
||||
|
||||
/* GPIO Register Offsets ************************************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -418,9 +418,9 @@
|
|||
# define TIVA_GPIONAHB_BASE (TIVA_PERIPH1_BASE + 0x64000) /* -0x64fff: GPIO Port N (AHB aperture) */
|
||||
# define TIVA_GPIOPAHB_BASE (TIVA_PERIPH1_BASE + 0x65000) /* -0x65fff: GPIO Port P (AHB aperture) */
|
||||
# define TIVA_GPIOQAHB_BASE (TIVA_PERIPH1_BASE + 0x66000) /* -0x66fff: GPIO Port Q (AHB aperture) */
|
||||
# define TIVA_GPIORRHB_BASE (TIVA_PERIPH1_BASE + 0x67000) /* -0x67fff: GPIO Port R (AHB aperture) */
|
||||
# define TIVA_GPIOFSHB_BASE (TIVA_PERIPH1_BASE + 0x68000) /* -0x68fff: GPIO Port S (AHB aperture) */
|
||||
# define TIVA_GPIOFTHB_BASE (TIVA_PERIPH1_BASE + 0x69000) /* -0x69fff: GPIO Port T (AHB aperture) */
|
||||
# define TIVA_GPIORAHB_BASE (TIVA_PERIPH1_BASE + 0x67000) /* -0x67fff: GPIO Port R (AHB aperture) */
|
||||
# define TIVA_GPIOSAHB_BASE (TIVA_PERIPH1_BASE + 0x68000) /* -0x68fff: GPIO Port S (AHB aperture) */
|
||||
# define TIVA_GPIOTAHB_BASE (TIVA_PERIPH1_BASE + 0x69000) /* -0x69fff: GPIO Port T (AHB aperture) */
|
||||
/* -0xaefff: Reserved */
|
||||
# define TIVA_EEPROM_BASE (TIVA_PERIPH1_BASE + 0xaf000) /* -0xaffff: EEPROM and Key Locker */
|
||||
/* -0xb5fff: Reserved */
|
||||
|
|
|
|||
|
|
@ -436,8 +436,8 @@ VECTOR(tiva_compare2, TIVA_IRQ_COMPARE2) /* Vector 43: Analog Comparator 2 *
|
|||
VECTOR(tiva_syscon, TIVA_IRQ_SYSCON) /* Vector 44: System Control */
|
||||
VECTOR(tiva_flashcon, TIVA_IRQ_FLASHCON) /* Vector 45: FLASH and EEPROM Control */
|
||||
VECTOR(tiva_gpiof, TIVA_IRQ_GPIOF) /* Vector 46: GPIO Port F */
|
||||
VECTOR(tiva_gpiof, TIVA_IRQ_GPIOG) /* Vector 47: GPIO Port G */
|
||||
VECTOR(tiva_gpiof, TIVA_IRQ_GPIOH) /* Vector 48: GPIO Port H */
|
||||
VECTOR(tiva_gpiog, TIVA_IRQ_GPIOG) /* Vector 47: GPIO Port G */
|
||||
VECTOR(tiva_gpioh, TIVA_IRQ_GPIOH) /* Vector 48: GPIO Port H */
|
||||
VECTOR(tiva_uart2, TIVA_IRQ_UART2) /* Vector 49: UART 2 */
|
||||
|
||||
VECTOR(tiva_ssi1, TIVA_IRQ_SSI1) /* Vector 50: SSI 1 */
|
||||
|
|
|
|||
|
|
@ -115,9 +115,7 @@ CONFIG_ARCH_HAVE_FPU=y
|
|||
#
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
|
||||
CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set
|
||||
|
|
@ -158,7 +156,7 @@ CONFIG_TIVA_UART0=y
|
|||
# CONFIG_TIVA_UART5 is not set
|
||||
# CONFIG_TIVA_UART6 is not set
|
||||
# CONFIG_TIVA_UART7 is not set
|
||||
# CONFIG_SSI0_DISABLE is not set
|
||||
CONFIG_SSI0_DISABLE=y
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
# CONFIG_TIVA_ETHERNET is not set
|
||||
# CONFIG_TIVA_FLASH is not set
|
||||
|
|
@ -182,12 +180,6 @@ CONFIG_TIVA_DISABLE_GPIOJ_IRQS=y
|
|||
# CONFIG_TIVA_DISABLE_GPIOP_IRQS is not set
|
||||
# CONFIG_TIVA_DISABLE_GPIOQ_IRQS is not set
|
||||
|
||||
#
|
||||
# Tiva/Stellaris SSI Configuration
|
||||
#
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# Architecture Options
|
||||
#
|
||||
|
|
@ -297,7 +289,7 @@ CONFIG_INIT_ENTRYPOINT=y
|
|||
# CONFIG_INIT_FILEPATH is not set
|
||||
CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
CONFIG_TASK_NAME_SIZE=31
|
||||
CONFIG_MAX_TASKS=16
|
||||
# CONFIG_SCHED_HAVE_PARENT is not set
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
|
|
|
|||
Loading…
Reference in New Issue