diff --git a/arch/arm/include/armv7-m/irq.h b/arch/arm/include/armv7-m/irq.h index 5b05c1d682..226101cd92 100644 --- a/arch/arm/include/armv7-m/irq.h +++ b/arch/arm/include/armv7-m/irq.h @@ -44,6 +44,8 @@ * Included Files ****************************************************************************/ +#include + #include #ifndef __ASSEMBLY__ # include @@ -72,10 +74,84 @@ #ifdef CONFIG_NUTTX_KERNEL # define REG_EXC_RETURN (10) /* EXC_RETURN */ -# define SW_XCPT_REGS (11) +# define SW_INT_REGS (11) #else -# define SW_XCPT_REGS (10) +# define SW_INT_REGS (10) #endif + +/* If the MCU supports a floating point unit, then it will be necessary + * to save the state of the FPU status register and data registers on + * each context switch. These registers are not saved during interrupt + * level processing, however. So, as a consequence, floating point + * operations may NOT be performed in interrupt handlers. + * + * The FPU provides an extension register file containing 32 single- + * precision registers. These can be viewed as: + * + * - Sixteen 64-bit doubleword registers, D0-D15 + * - Thirty-two 32-bit single-word registers, S0-S31 + * S<2n> maps to the least significant half of D + * S<2n+1> maps to the most significant half of D. + */ + +#ifdef CONFIG_ARCH_FPU +# define REG_D0 (SW_INT_REGS+0) /* D0 */ +# define REG_S0 (SW_INT_REGS+0) /* S0 */ +# define REG_S1 (SW_INT_REGS+1) /* S1 */ +# define REG_D1 (SW_INT_REGS+2) /* D1 */ +# define REG_S2 (SW_INT_REGS+2) /* S2 */ +# define REG_S3 (SW_INT_REGS+3) /* S3 */ +# define REG_D2 (SW_INT_REGS+4) /* D2 */ +# define REG_S4 (SW_INT_REGS+4) /* S4 */ +# define REG_S5 (SW_INT_REGS+5) /* S5 */ +# define REG_D3 (SW_INT_REGS+6) /* D3 */ +# define REG_S6 (SW_INT_REGS+6) /* S6 */ +# define REG_S7 (SW_INT_REGS+7) /* S7 */ +# define REG_D4 (SW_INT_REGS+8) /* D4 */ +# define REG_S8 (SW_INT_REGS+8) /* S8 */ +# define REG_S9 (SW_INT_REGS+9) /* S9 */ +# define REG_D5 (SW_INT_REGS+10) /* D5 */ +# define REG_S10 (SW_INT_REGS+10) /* S10 */ +# define REG_S11 (SW_INT_REGS+11) /* S11 */ +# define REG_D6 (SW_INT_REGS+12) /* D6 */ +# define REG_S12 (SW_INT_REGS+12) /* S12 */ +# define REG_S13 (SW_INT_REGS+13) /* S13 */ +# define REG_D7 (SW_INT_REGS+14) /* D7 */ +# define REG_S14 (SW_INT_REGS+14) /* S14 */ +# define REG_S15 (SW_INT_REGS+15) /* S15 */ +# define REG_D8 (SW_INT_REGS+16) /* D8 */ +# define REG_S16 (SW_INT_REGS+16) /* S16 */ +# define REG_S17 (SW_INT_REGS+17) /* S17 */ +# define REG_D9 (SW_INT_REGS+18) /* D9 */ +# define REG_S18 (SW_INT_REGS+18) /* S18 */ +# define REG_S19 (SW_INT_REGS+19) /* S19 */ +# define REG_D10 (SW_INT_REGS+20) /* D10 */ +# define REG_S20 (SW_INT_REGS+20) /* S20 */ +# define REG_S21 (SW_INT_REGS+21) /* S21 */ +# define REG_D11 (SW_INT_REGS+22) /* D11 */ +# define REG_S22 (SW_INT_REGS+22) /* S22 */ +# define REG_S23 (SW_INT_REGS+23) /* S23 */ +# define REG_D12 (SW_INT_REGS+24) /* D12 */ +# define REG_S24 (SW_INT_REGS+24) /* S24 */ +# define REG_S25 (SW_INT_REGS+25) /* S25 */ +# define REG_D13 (SW_INT_REGS+26) /* D13 */ +# define REG_S26 (SW_INT_REGS+26) /* S26 */ +# define REG_S27 (SW_INT_REGS+27) /* S27 */ +# define REG_D14 (SW_INT_REGS+28) /* D14 */ +# define REG_S28 (SW_INT_REGS+28) /* S28 */ +# define REG_S29 (SW_INT_REGS+29) /* S29 */ +# define REG_D15 (SW_INT_REGS+30) /* D15 */ +# define REG_S30 (SW_INT_REGS+30) /* S30 */ +# define REG_S31 (SW_INT_REGS+31) /* S31 */ +# DEFINE REG_FPSCR (SW_INT_REGS+32) /* Floating point status and control */ +# define SW_FPU_REGS (33) +#else +# define SW_FPU_REGS (0) +#endif + +/* The total number of registers saved by software */ + +#define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS) #define SW_XCPT_SIZE (4 * SW_XCPT_REGS) /* On entry into an IRQ, the hardware automatically saves the following diff --git a/arch/arm/src/armv7-m/nvic.h b/arch/arm/src/armv7-m/nvic.h index ed66e06e92..b0b08ddefc 100644 --- a/arch/arm/src/armv7-m/nvic.h +++ b/arch/arm/src/armv7-m/nvic.h @@ -204,6 +204,11 @@ #define NVIC_ISAR4_OFFSET 0x0d70 /* ISA feature register 4 */ #define NVIC_CPACR_OFFSET 0x0d88 /* Coprocessor Access Control Register */ #define NVIC_STIR_OFFSET 0x0f00 /* Software trigger interrupt register */ +#define NVIC_FPCCR_OFFSET 0x0f34 /* Floating-point Context Control Register */ +#define NVIC_FPCAR_OFFSET 0x0f38 /* Floating-point Context Address Register */ +#define NVIC_FPDSCR_OFFSET 0x0f3c /* Floating-point Default Status Control Register */ +#define NVIC_MVFR0_OFFSET 0x0f40 /* Media and VFP Feature Register 0 */ +#define NVIC_MVFR1_OFFSET 0x0f44 /* Media and VFP Feature Register 1 */ #define NVIC_PID4_OFFSET 0x0fd0 /* Peripheral identification register (PID4) */ #define NVIC_PID5_OFFSET 0x0fd4 /* Peripheral identification register (PID5) */ #define NVIC_PID6_OFFSET 0x0fd8 /* Peripheral identification register (PID6) */