diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c
index 874ef1c96a..33540549c8 100644
--- a/arch/arm/src/lpc17xx/lpc17_ethernet.c
+++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c
@@ -714,10 +714,10 @@ static int lpc17_transmit(struct lpc17_driver_s *priv)
              (priv->lp_dev.d_len - 1);
 
   /* Copy the packet data into the Tx buffer assignd to this descriptor.  It
-   * should fit because each packet buffer is the MTU size and breaking up larger
-   * TCP messasges is handled by higher level logic.  The hardware does, however,t
-   * support breaking up larger messages into many fragments, however, that
-   * capability is not exploited here.
+   * should fit because each packet buffer is the MTU size and breaking up
+   * largerTCP messasges is handled by higher level logic.  The hardware
+   * does, however, support breaking up larger messages into many fragments,
+   * however, that capability is not exploited here.
    *
    * This would be a great performance improvement:  Remove the buffer from
    * the lp_dev structure and replace it a pointer directly into the EMAC
@@ -744,7 +744,8 @@ static int lpc17_transmit(struct lpc17_driver_s *priv)
 
   /* Setup the TX timeout watchdog (perhaps restarting the timer) */
 
-  (void)wd_start(priv->lp_txtimeout, LPC17_TXTIMEOUT, lpc17_txtimeout, 1, (uint32_t)priv);
+  (void)wd_start(priv->lp_txtimeout, LPC17_TXTIMEOUT, lpc17_txtimeout,
+                 1, (uint32_t)priv);
   return OK;
 }
 
diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx/lpc17_irq.c
index 886bb74808..59802d87d6 100755
--- a/arch/arm/src/lpc17xx/lpc17_irq.c
+++ b/arch/arm/src/lpc17xx/lpc17_irq.c
@@ -259,6 +259,33 @@ static int lpc17_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
   return OK;
 }
 
+/****************************************************************************
+ * Name: lpc17_clrpend
+ *
+ * Description:
+ *  Clear a pending interrupt.
+ *
+ ****************************************************************************/
+
+static inline void lpc17_clrpend(int irq)
+{
+#if 0 /* Necessary? */
+  /* Check for external interrupt */
+
+  if (irq >= LPC17_IRQ_EXTINT)
+    {
+      if (irq < (LPC17_IRQ_EXTINT+32))
+        {
+          putreg32(1 << (irq - LPC17_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND);
+        }
+      else if (irq < LPC17_IRQ_NIRQS)
+        {
+          putreg32(1 << (irq - LPC17_IRQ_EXTINT - 32), NVIC_IRQ32_63_CLRPEND);
+        }
+    }
+#endif
+}
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -426,6 +453,7 @@ void up_enable_irq(int irq)
 void up_maskack_irq(int irq)
 {
   up_disable_irq(irq);
+  lpc17_clrpend(irq);
 }
 
 /****************************************************************************
diff --git a/arch/arm/src/lpc17xx/lpc17_vectors.S b/arch/arm/src/lpc17xx/lpc17_vectors.S
index 8498dd87ac..ae36da345f 100755
--- a/arch/arm/src/lpc17xx/lpc17_vectors.S
+++ b/arch/arm/src/lpc17xx/lpc17_vectors.S
@@ -295,7 +295,7 @@ lpc17_common:
 2:
 	msr		msp, r1					/* Recover the return MSP value */
 
-	/* Do we need to restore interrupts? */
+	/* Do we need to restore interrupts? Why not just: msr primask, r3 */
 
 	tst		r3, #1					/* PRIMASK bit 1=1 means that interrupts are masked */
 	bne		3f