Add M16C info
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1483 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -51,10 +51,150 @@
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* Definitions
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************************************************************************************/
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/* IRQ numbers -- to be provided */
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/* IRQ numbers **********************************************************************/
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#define NR_IRQS 1 /* Total number of supported IRQs */
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#define M16C_SYSTIMER_IRQ 1
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/* Fixed vector table */
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#define M16C_UNDEFINST_IRQ 0 /* fffdc: Undefined instruction */
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#define M16C_OVERFLOW_IRQ 1 /* fffe0: Overflow */
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#define M16C_BRK_IRQ 2 /* fffe4: BRK instruction */
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#define M16C_ADDRMATCH_IRQ 3 /* fffe8: Address match */
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#ifdef CONFIG_M16C_DEBUGGER
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# define M16C_SSTEP_IRQ 4 /* fffec: Single step */
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# define M16C_WDOG_IRQ 5 /* ffff0: Watchdog timer */
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# define M16C_DBC_IRQ 6 /* ffff4: DBC */
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# define M16C_NMI_IRQ 7 /* ffff8: NMI */
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# define M16C_RESET_IRQ 8 /* ffffc: Reset */
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# define _LAST_FIXED 8
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#else
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# define M16C_WDOG_IRQ 4 /* ffff0: Watchdog timer */
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# define M16C_NMI_IRQ 5 /* ffff8: NMI */
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# define M16C_RESET_IRQ 6 /* ffffc: Reset */
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# define _LAST_FIXED 6
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#endif
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/* Variable vector table (fixed at address 0xffd00) */
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#ifdef CONFIG_M16C_SWINTS
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# define M16C_BRK_IRQ (_LAST_FIXED+1) /* ffd00: BRK instruction */
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# define M16C_SWINT0_IRQ M16C_BRK_IRQ /* S/W interrupt 0 */
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# define M16C_INT3_IRQ (_LAST_FIXED+2) /* ffd10: INT3 */
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# define M16C_SWINT4_IRQ M16C_INT3_IRQ /* S/W interrupt 4 */
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# define M16C_SWINT5_IRQ (_LAST_FIXED+3) /* ffd14: Reserved / S/W interrupt 5 */
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# define M16C_SWINT6_IRQ (_LAST_FIXED+4) /* ffd18: Reserved / S/W interrupt 6 */
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# define M16C_SWINT7_IRQ (_LAST_FIXED+5) /* ffd1c: Reserved / S/W interrupt 7 */
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# define M16C_INT5_IRQ (_LAST_FIXED+6) /* ffd20: INT5 */
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# define M16C_SWINT8_IRQ M16C_INT5_IRQ /* S/W interrupt 8 */
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# define M16C_INT4_IRQ (_LAST_FIXED+7) /* ffd24: INT4 */
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# define M16C_SWINT9_IRQ M16C_INT4_IRQ /* S/W interrupt 9 */
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# define M16C_UART2BCD_IRQ (_LAST_FIXED+8) /* ffd28: UART2 bus collision detection */
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# define M16C_SWINT10_IRQ M16C_UART2BCD_IRQ /* S/W interrupt 10 */
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# define M16C_DMA0_IRQ (_LAST_FIXED+9) /* ffd2c: DMA0 */
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# define M16C_SWINT11_IRQ M16C_DMA0_IRQ /* S/W interrupt 11 */
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# define M16C_DMA1_IRQ (_LAST_FIXED+10) /* ffd30: DMA1 */
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# define M16C_SWINT12_IRQ M16C_DMA1_IRQ /* S/W interrupt 12 */
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# define M16C_KEYINP_IRQ (_LAST_FIXED+11) /* ffd34: Key input interrupt */
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# define M16C_SWINT13_IRQ M16C_KEYINP_IRQ /* S/W interrupt 13 */
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# define M16C_ADC_IRQ (_LAST_FIXED+12) /* ffd38: A-D */
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# define M16C_SWINT14_IRQ M16C_ADC_IRQ /* S/W interrupt 14 */
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# define M16C_UARTXNAK_IRQ (_LAST_FIXED+13) /* ffd3c UART2 transmit/NACK2 */
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# define M16C_SWINT15_IRQ M16C_UARTNAK_IRQ /* S/W interrupt 15 */
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# define M16C_UARTRACK_IRQ (_LAST_FIXED+14) /* ffd40: UART2 receive/ACK2 */
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# define M16C_SWINT16_IRQ M16C_UARTRACK_IRQ /* S/W interrupt 16 */
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# define M16C_UART0XMT_IRQ (_LAST_FIXED+15) /* ffd44: UART0 transmit */
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# define M16C_SWINT17_IRQ M16C_UART0XMT_IRQ /* S/W interrupt 17 */
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# define M16C_UART0RCV_IRQ (_LAST_FIXED+16) /* ffd48: UART0 receive */
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# define M16C_SWINT18_IRQ M16C_UART0RCV_IRQ /* S/W interrupt 18 */
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# define M16C_UART1XMT_IRQ (_LAST_FIXED+17) /* ffd4c: UART1 transmit */
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# define M16C_SWINT19_IRQ M16C_UART1XMT_IRQ /* S/W interrupt 19 */
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# define M16C_UART1RCV_IRQ (_LAST_FIXED+18) /* ffd50: UART1 receive */
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# define M16C_SWINT20_IRQ M16C_UART1RCV_IRQ /* S/W interrupt 20 */
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# define M16C_TMRA0_IRQ (_LAST_FIXED+19) /* ffd54: Timer A0 */
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# define M16C_SWINT21_IRQ M16C_TMRA0_IRQ /* S/W interrupt 21 */
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# define M16C_TMRA1_IRQ (_LAST_FIXED+20) /* ffd58: Timer A1 */
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# define M16C_SWINT22_IRQ M16C_TMRA1_IRQ /* S/W interrupt 22 */
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# define M16C_TMRA2_IRQ (_LAST_FIXED+21) /* ffd5c: Timer A2 */
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# define M16C_SWINT23_IRQ M16C_TMRA2_IRQ /* S/W interrupt 23 */
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# define M16C_TMRA3_IRQ (_LAST_FIXED+22) /* ffd60: Timer A3 */
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# define M16C_SWINT24_IRQ M16C_TMRA3_IRQ /* S/W interrupt 24 */
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# define M16C_TMRA4_IRQ (_LAST_FIXED+23) /* ffd64: Timer A4 */
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# define M16C_SWINT25_IRQ M16C_TMRA4_IRQ /* S/W interrupt 25 */
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# define M16C_TMRB0_IRQ (_LAST_FIXED+24) /* ffd68: Timer B0 */
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# define M16C_SWINT26_IRQ M16C_TMRB0_IRQ /* S/W interrupt 26 */
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# define M16C_TMRB1_IRQ (_LAST_FIXED+25) /* ffd6c: Timer B1 */
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# define M16C_SWINT27_IRQ M16C_TMRB1_IRQ /* S/W interrupt 27 */
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# define M16C_TMRB2_IRQ (_LAST_FIXED+26) /* ffd70: Timer B2 */
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# define M16C_SWINT28_IRQ M16C_TMRB2_IRQ /* S/W interrupt 28 */
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# define M16C_INT0_IRQ (_LAST_FIXED+27) /* ffd74: INT0 */
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# define M16C_SWINT29_IRQ M16C_INT0_IRQ /* S/W interrupt 29 */
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# define M16C_INT1_IRQ (_LAST_FIXED+28) /* ffd78: INT1 */
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# define M16C_SWINT30_IRQ M16C_INT1_IRQ /* S/W interrupt 30 */
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# define M16C_SWINT31_IRQ (_LAST_FIXED+29) /* ffd7c: Reserved / S/W interrupt 31 */
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# define M16C_SWINT32_IRQ (_LAST_FIXED+30) /* ffd80: S/W interrupt 32 */
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# define M16C_SWINT33_IRQ (_LAST_FIXED+31) /* ffd84: S/W interrupt 33 */
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# define M16C_SWINT34_IRQ (_LAST_FIXED+32) /* ffd88: S/W interrupt 34 */
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# define M16C_SWINT35_IRQ (_LAST_FIXED+33) /* ffd8c: S/W interrupt 35 */
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# define M16C_SWINT36_IRQ (_LAST_FIXED+34) /* ffd90: S/W interrupt 36 */
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# define M16C_SWINT37_IRQ (_LAST_FIXED+35) /* ffd94: S/W interrupt 37 */
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# define M16C_SWINT38_IRQ (_LAST_FIXED+36) /* ffd98: S/W interrupt 38 */
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# define M16C_SWINT39_IRQ (_LAST_FIXED+37) /* ffd9c: S/W interrupt 39 */
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# define M16C_SWINT40_IRQ (_LAST_FIXED+38) /* ffda0: S/W interrupt 40 */
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# define M16C_SWINT41_IRQ (_LAST_FIXED+39) /* ffda4: S/W interrupt 41 */
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# define M16C_SWINT42_IRQ (_LAST_FIXED+40) /* ffda8: S/W interrupt 42 */
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# define M16C_SWINT43_IRQ (_LAST_FIXED+41) /* ffdac: S/W interrupt 43 */
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# define M16C_SWINT44_IRQ (_LAST_FIXED+42) /* ffdb0: S/W interrupt 44 */
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# define M16C_SWINT45_IRQ (_LAST_FIXED+43) /* ffdb4: S/W interrupt 45 */
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# define M16C_SWINT46_IRQ (_LAST_FIXED+44) /* ffdb8: S/W interrupt 46 */
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# define M16C_SWINT47_IRQ (_LAST_FIXED+45) /* ffdbc: S/W interrupt 47 */
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# define M16C_SWINT48_IRQ (_LAST_FIXED+46) /* ffdc0: S/W interrupt 48 */
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# define M16C_SWINT49_IRQ (_LAST_FIXED+47) /* ffdc4: S/W interrupt 49 */
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# define M16C_SWINT50_IRQ (_LAST_FIXED+48) /* ffdc8: S/W interrupt 50 */
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# define M16C_SWINT51_IRQ (_LAST_FIXED+49) /* ffdcc: S/W interrupt 51 */
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# define M16C_SWINT52_IRQ (_LAST_FIXED+50) /* ffdd0: S/W interrupt 52 */
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# define M16C_SWINT53_IRQ (_LAST_FIXED+51) /* ffdd4: S/W interrupt 53 */
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# define M16C_SWINT54_IRQ (_LAST_FIXED+52) /* ffdd8: S/W interrupt 54 */
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# define M16C_SWINT55_IRQ (_LAST_FIXED+53) /* ffddc: S/W interrupt 55 */
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# define M16C_SWINT56_IRQ (_LAST_FIXED+54) /* ffde0: S/W interrupt 56 */
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# define M16C_SWINT57_IRQ (_LAST_FIXED+55) /* ffde4: S/W interrupt 57 */
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# define M16C_SWINT58_IRQ (_LAST_FIXED+56) /* ffde8: S/W interrupt 58 */
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# define M16C_SWINT59_IRQ (_LAST_FIXED+57) /* ffdec: S/W interrupt 59 */
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# define M16C_SWINT60_IRQ (_LAST_FIXED+58) /* ffdf0: S/W interrupt 60 */
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# define M16C_SWINT61_IRQ (_LAST_FIXED+59) /* ffdf4: S/W interrupt 61 */
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# define M16C_SWINT62_IRQ (_LAST_FIXED+60) /* ffdf8: S/W interrupt 62 */
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# define M16C_SWINT63_IRQ (_LAST_FIXED+61) /* ffdfc: S/W interrupt 63 */
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# define NR_IRQS (_LAST_FIXED+62) /* Total number of supported IRQs */
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#else
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# define M16C_BRK_IRQ (_LAST_FIXED+1) /* ffd00: BRK instruction */
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# define M16C_INT3_IRQ (_LAST_FIXED+2) /* ffd10: INT3 */
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# define M16C_INT5_IRQ (_LAST_FIXED+3) /* ffd20: INT5 */
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# define M16C_INT4_IRQ (_LAST_FIXED+4) /* ffd24: INT4 */
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# define M16C_UART2BCD_IRQ (_LAST_FIXED+5) /* ffd28: UART2 bus collision detection */
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# define M16C_DMA0_IRQ (_LAST_FIXED+6) /* ffd2c: DMA0 */
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# define M16C_DMA1_IRQ (_LAST_FIXED+7) /* ffd30: DMA1 */
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# define M16C_KEYINP_IRQ (_LAST_FIXED+8) /* ffd34: Key input interrupt */
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# define M16C_ADC_IRQ (_LAST_FIXED+9) /* ffd38: A-D */
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# define M16C_UARTXNAK_IRQ (_LAST_FIXED+10) /* ffd3c UART2 transmit/NACK2 */
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# define M16C_UARTRACK_IRQ (_LAST_FIXED+11) /* ffd40: UART2 receive/ACK2 */
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# define M16C_UART0XMT_IRQ (_LAST_FIXED+12) /* ffd44: UART0 transmit */
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# define M16C_UART0RCV_IRQ (_LAST_FIXED+13) /* ffd48: UART0 receive */
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# define M16C_UART1XMT_IRQ (_LAST_FIXED+14) /* ffd4c: UART1 transmit */
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# define M16C_UART1RCV_IRQ (_LAST_FIXED+15) /* ffd50: UART1 receive */
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# define M16C_TMRA0_IRQ (_LAST_FIXED+16) /* ffd54: Timer A0 */
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# define M16C_TMRA1_IRQ (_LAST_FIXED+17) /* ffd58: Timer A1 */
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# define M16C_TMRA2_IRQ (_LAST_FIXED+18) /* ffd5c: Timer A2 */
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# define M16C_TMRA3_IRQ (_LAST_FIXED+19) /* ffd60: Timer A3 */
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# define M16C_TMRA4_IRQ (_LAST_FIXED+20) /* ffd64: Timer A4 */
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# define M16C_TMRB0_IRQ (_LAST_FIXED+21) /* ffd68: Timer B0 */
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# define M16C_TMRB1_IRQ (_LAST_FIXED+22) /* ffd6c: Timer B1 */
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# define M16C_TMRB2_IRQ (_LAST_FIXED+23) /* ffd70: Timer B2 */
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# define M16C_INT0_IRQ (_LAST_FIXED+24) /* ffd74: INT0 */
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# define M16C_INT1_IRQ (_LAST_FIXED+25) /* ffd78: INT1 */
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# define NR_IRQS (_LAST_FIXED+26 /* Total number of supported IRQs */
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#endif
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#define M16C_SYSTIMER_IRQ M16C_TMRA0_IRQ
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/* IRQ Stack Frame Format. The SH-1 has a push down stack. The PC
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* and SR are pushed by hardware at the time an IRQ is taken.
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@ -62,8 +202,8 @@
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/* To be provided */
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#define XCPTCONTEXT_REGS (1)
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#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
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#define XCPTCONTEXT_REGS (1)
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#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
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/************************************************************************************
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* Public Types
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