arm64_sync_exc: Use temporaries x9/x10 instead of x0/x1
Why? Because this allows optimizing the user system call path in such a way that the parameter registers don't have to be read from the saved integer register context when the system call is executed.
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@ -143,7 +143,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
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/* Current EL with SP0 / Synchronous */
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.align 7
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arm64_enter_exception x0, x1
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arm64_enter_exception x9, x10
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b arm64_sync_exc
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/* Current EL with SP0 / IRQ */
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@ -167,7 +167,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
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/* Current EL with SPx / Synchronous */
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.align 7
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arm64_enter_exception x0, x1
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arm64_enter_exception x9, x10
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b arm64_sync_exc
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/* Current EL with SPx / IRQ */
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@ -191,7 +191,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
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/* Lower EL using AArch64 / Synchronous */
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.align 7
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arm64_enter_exception x0, x1
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arm64_enter_exception x9, x10
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b arm64_sync_exc
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/* Lower EL using AArch64 / IRQ */
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@ -187,18 +187,18 @@ SECTION_FUNC(text, arm64_sync_exc)
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/* checking the EC value to see which exception need to be handle */
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#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
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mrs x0, esr_el3
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mrs x9, esr_el3
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#else
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mrs x0, esr_el1
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mrs x9, esr_el1
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#endif
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lsr x1, x0, #26
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lsr x10, x9, #26
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#ifdef CONFIG_ARCH_FPU
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/* fpu trap */
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cmp x1, #0x07 /*Access to SIMD or floating-point */
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cmp x10, #0x07 /* Access to SIMD or floating-point */
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bne 1f
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mov x0, sp
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mov x0, sp /* x0 = context */
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bl arm64_fpu_trap
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/* when the fpu trap is handled */
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@ -208,7 +208,7 @@ SECTION_FUNC(text, arm64_sync_exc)
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#endif
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/* 0x15 = SVC system call */
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cmp x1, #0x15
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cmp x10, #0x15
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/* if this is a svc call ?*/
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@ -248,6 +248,7 @@ SECTION_FUNC(text, arm64_sync_exc)
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*/
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mov x0, sp /* x0 = reg frame */
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/* Call arm64_syscall() on the user stack */
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bl arm64_syscall /* Call the handler */
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