Xtensa ESP32: Update APP CPU startup logic to match current Expressif example code.

arch/xtensa/src/esp32/esp32_cpustart.c

@@ -53,15 +53,13 @@
 #include "sched/sched.h"
 #include "xtensa.h"
 #include "chip/esp32_dport.h"
+#include "chip/esp32_rtccntl.h"
 #include "esp32_region.h"
 #include "esp32_cpuint.h"
 #include "esp32_smp.h"
 
 #ifdef CONFIG_SMP
 
-#warning REVISIT Need ets_set_appcpu_boot_addr() prototype
-void ets_set_appcpu_boot_addr(uint32_t);
-
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -69,6 +67,14 @@ void ets_set_appcpu_boot_addr(uint32_t);
 static volatile bool g_appcpu_started;
 static sem_t g_appcpu_interlock;
 
+/****************************************************************************
+ * ROM function prototypes
+ ****************************************************************************/
+
+void Cache_Flush(int cpu);
+void Cache_Read_Enable(int cpu);
+void ets_set_appcpu_boot_addr(uint32_t start);
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -259,6 +265,23 @@ int up_cpu_start(int cpu)
       sem_init(&g_appcpu_interlock, 0, 0);
       sem_setprotocol(&g_appcpu_interlock, SEM_PRIO_NONE);
 
+      /* Flush and enable I-cache for APP CPU */
+
+      Cache_Flush(cpu);
+      Cache_Read_Enable(cpu);
+
+      /* Unstall the APP CPU */
+
+      regval  = getreg32(RTC_CNTL_SW_CPU_STALL_REG);
+      regval &= ~RTC_CNTL_SW_STALL_APPCPU_C1_M;
+      putreg32(regval, RTC_CNTL_SW_CPU_STALL_REG);
+
+      regval  = getreg32(RTC_CNTL_OPTIONS0_REG);
+      regval &= ~RTC_CNTL_SW_STALL_APPCPU_C0_M;
+      putreg32(regval, RTC_CNTL_OPTIONS0_REG);
+
+      /* Enable clock gating for the APP CPU */
+
       regval  = getreg32(DPORT_APPCPU_CTRL_B_REG);
       regval |= DPORT_APPCPU_CLKGATE_EN;
       putreg32(regval, DPORT_APPCPU_CTRL_B_REG);
@@ -267,6 +290,8 @@ int up_cpu_start(int cpu)
       regval &= ~DPORT_APPCPU_RUNSTALL;
       putreg32(regval, DPORT_APPCPU_CTRL_C_REG);
 
+      /* Reset the APP CPU */
+
       regval  = getreg32(DPORT_APPCPU_CTRL_A_REG);
       regval |= DPORT_APPCPU_RESETTING;
       putreg32(regval, DPORT_APPCPU_CTRL_A_REG);
@@ -279,7 +304,7 @@ int up_cpu_start(int cpu)
 
       ets_set_appcpu_boot_addr((uint32_t)__cpu1_start);
 
-      /* And way for the initial task to run on CPU1 */
+      /* And wait for the initial task to run on CPU1 */
 
       while (!g_appcpu_started)
         {

configs/esp32-core/README.txt

@@ -636,6 +636,29 @@ NOTES:
 
     NOTES:
 
+    1. Uses the CP2102 USB/Serial converter for the serial console.
+
+    2. I have only tested this in IRAM with UART reconfiguration disabled.
+       See "Sample Debug Steps".  In that case, NuttX is started via GDB.
+       It has, however, been reported to me that this configuration also
+       runs when written to address 0x1000 of FLASH with the esptool.py
+       (as described above).  Then NuttX is started via the second level
+       bootloader.  I cannot vouch for that since I have never tried it.
+
+    3. There are open clocking issues.  Currently clock configuration
+       logic is disabled because I don't have the technical information
+       to provide that logic -- hopefully that is coming.  As a
+       consequence, whatever clock setup was left when NuttX started is
+       used.  For the case of execution out of IRAM with GDB, the
+       settings in configs/esp32-core/include/board.h work.  To check
+       the timing, I use a stop watch and:
+
+         nsh> sleep 60
+
+       If the timing is correct in the board.h header file, the value
+       timed with the stop watch should be about 60 seconds.  If not,
+       change the frequency in the board.h header file.
+
   smp:
 
     Another NSH configuration, similar to nsh, but also enables