arch/arm: add support for chip to replace the default vector table
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
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17c102c10c
commit
4e2b77cb04
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@ -1119,6 +1119,13 @@ config ARCH_RAMFUNCS
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so that FLASH can be reconfigured while the MCU executes out of
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SRAM.
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config ARCH_HAVE_CUSTOM_VECTORS
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bool
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default n
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---help---
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If ARCH_HAVE_CUSTOM_VECTORS is defined, Chip should provide vectors
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table as an optimization.
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config ARCH_HAVE_RAMVECTORS
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bool
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default n
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@ -26,9 +26,13 @@ CMN_ASRCS += arm_exception.S arm_saveusercontext.S
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CMN_CSRCS += arm_cpuinfo.c arm_doirq.c arm_hardfault.c arm_initialstate.c
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CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_svcall.c
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CMN_CSRCS += arm_systemreset.c arm_tcbinfo.c arm_vectors.c
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CMN_CSRCS += arm_systemreset.c arm_tcbinfo.c
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CMN_CSRCS += arm_trigger_irq.c
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ifneq ($(CONFIG_ARCH_HAVE_CUSTOM_VECTORS),y)
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CMN_CSRCS += arm_vectors.c
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endif
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ifneq ($(filter y,$(CONFIG_DEBUG_FEATURES)$(CONFIG_ARM_COREDUMP_REGION)),)
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CMN_CSRCS += arm_dumpnvic.c
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endif
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@ -29,7 +29,11 @@ CMN_CSRCS += arm_hardfault.c arm_initialstate.c arm_itm.c
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CMN_CSRCS += arm_memfault.c arm_perf.c
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CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
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CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_tcbinfo.c
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CMN_CSRCS += arm_trigger_irq.c arm_usagefault.c arm_vectors.c arm_dbgmonitor.c
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CMN_CSRCS += arm_trigger_irq.c arm_usagefault.c arm_dbgmonitor.c
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ifneq ($(CONFIG_ARCH_HAVE_CUSTOM_VECTORS),y)
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CMN_CSRCS += arm_vectors.c
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endif
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ifeq ($(CONFIG_ARMV7M_SYSTICK),y)
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CMN_CSRCS += arm_systick.c
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@ -30,7 +30,11 @@ CMN_CSRCS += arm_memfault.c arm_perf.c arm_sau.c
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CMN_CSRCS += arm_schedulesigaction.c arm_securefault.c arm_secure_irq.c
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CMN_CSRCS += arm_sigdeliver.c arm_svcall.c
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CMN_CSRCS += arm_systemreset.c arm_tcbinfo.c
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CMN_CSRCS += arm_trigger_irq.c arm_usagefault.c arm_vectors.c arm_dbgmonitor.c
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CMN_CSRCS += arm_trigger_irq.c arm_usagefault.c arm_dbgmonitor.c
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ifneq ($(CONFIG_ARCH_HAVE_CUSTOM_VECTORS),y)
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CMN_CSRCS += arm_vectors.c
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endif
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ifeq ($(CONFIG_ARMV8M_SYSTICK),y)
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CMN_CSRCS += arm_systick.c
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