OrgApache/incubator-nuttx
OrgApache
/
incubator-nuttx
mirror of https://github.com/apache/incubator-nuttx.git
1
0
Fork 0
Code Issues Releases Wiki Activity

STM32L-Discovery LCD driver is code compele but untested

This commit is contained in:
Gregory Nutt 2013-05-23 15:23:29 -06:00
parent db128e488e
commit 4b2e2e6edc
2 changed files with 19 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
arch/arm/src/stm32/Kconfig
View File

@ -500,7 +500,7 @@ config STM32_CAN1
default n
select CAN
select STM32_CAN
depends on !STM32_VALUELINE
depends on !STM32_VALUELINE && !STM32_STM32L15XX
config STM32_CAN2
bool "CAN2"
@ -586,11 +586,6 @@ config STM32_I2C3
depends on STM32_STM32F20XX || STM32_STM32F40XX
select STM32_I2C
config STM32_IWDG
bool "IWDG"
default n
select WATCHDOG
config STM32_OTGFS
bool "OTG FS"
default n
@ -664,6 +659,7 @@ config STM32_SYSCFG
config STM32_TIM1
bool "TIM1"
default n
depends on !STM32_STM32L15XX
config STM32_TIM2
bool "TIM2"
@ -693,7 +689,7 @@ config STM32_TIM7
config STM32_TIM8
bool "TIM8"
default n
depends on !STM32_VALUELINE
depends on !STM32_VALUELINE && !STM32_STM32L15XX
config STM32_TIM9
bool "TIM9"
@ -767,14 +763,14 @@ config STM32_USART3
config STM32_UART4
bool "UART4"
default n
depends on !STM32_STM32F30XX
depends on !STM32_STM32F30XX &&!STM32_STM32L15XX
select ARCH_HAVE_UART4
select STM32_USART
config STM32_UART5
bool "UART5"
default n
depends on !STM32_STM32F30XX
depends on !STM32_STM32F30XX &&!STM32_STM32L15XX
select ARCH_HAVE_UART5
select STM32_USART
@ -805,6 +801,16 @@ config STM32_USB
depends on (STM32_STM32F10XX && !STM32_VALUELINE) || STM32_STM32L15XX || STM32_STM32F30XX
select USBDEV
config STM32_LCD
bool "Segment LCD"
default n
depends on STM32_STM32L15XX
config STM32_IWDG
bool "IWDG"
default n
select WATCHDOG
config STM32_WWDG
bool "WWDG"
default n

8
arch/arm/src/stm32/chip/stm32_lcd.h
View File

@ -125,7 +125,7 @@
# define LCD_CR_BIAS_1TO4 (0 << LCD_CR_BIAS_SHIFT) /* 00: Bias 1/4 */
# define LCD_CR_BIAS_1TO2 (1 << LCD_CR_BIAS_SHIFT) /* 01: Bias 1/2 */
# define LCD_CR_BIAS_1TO3 (2 << LCD_CR_BIAS_SHIFT) /* 10: Bias 1/3 */
#define LCD_CR_MUX_SEG (1 << 7) /* Bit 7: Mux segment enable
#define LCD_CR_MUX_SEG (1 << 7) /* Bit 7: Mux segment enable */
/* Bits 8-31 Reserved */
/* LCD frame control register */
@ -181,7 +181,7 @@
# define LCD_FCR_PS_DIV8192 (13 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/8192 */
# define LCD_FCR_PS_DIV16384 (14 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/16384 */
# define LCD_FCR_PS_DIV32768 (15 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/32768 */
/* Bits 26-31 Reserved
/* Bits 26-31 Reserved */
/* LCD status register */
@ -191,14 +191,14 @@
#define LCD_SR_UDD (1 << 3) /* Bit 3: Update Display Done */
#define LCD_SR_RDY (1 << 4) /* Bit 4: Ready flag */
#define LCD_SR_FCRSF (1 << 5) /* Bit 5: LCD Frame Control Register Synchronization flag */
/* Bits 6-31 Reserved
/* Bits 6-31 Reserved */
/* LCD clear register */
/* Bit 0 Reserved */
#define LCD_CLR_SOFC (1 << 1) /* Bit 1: Start of frame flag clear */
/* Bit 2 Reserved */
#define LCD_CLR_UDDC (1 << 2) /* Bit 3: Update display done clear
#define LCD_CLR_UDDC (1 << 2) /* Bit 3: Update display done clear */
/* Bits 31:2-31 Reserved */
/* LCD display memory, COMn, S00-S31 */