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stm32f0l0g0: remove references to non-existent ADCs, only ADC1 present on STM32 M0/M0+ devices

This commit is contained in:
raiden00pl 2022-07-15 14:42:16 +02:00 committed by Alan Carvalho de Assis
parent 9276e41321
commit 47e29d9402
5 changed files with 7 additions and 14 deletions
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13
arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
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@ -75,18 +75,11 @@
* Pre-processor Definitions
****************************************************************************/
#define STM32_ADC1_OFFSET 0x0000
#define STM32_ADC2_OFFSET 0x0100
#define STM32_ADC3_OFFSET 0x0000
#define STM32_ADC4_OFFSET 0x0100
#define STM32_ADCCMN_OFFSET 0x0300
#define STM32_ADC1_BASE (STM32_ADC1_OFFSET+STM32_ADC12_BASE) /* ADC1 Master ADC */
#define STM32_ADC2_BASE (STM32_ADC2_OFFSET+STM32_ADC12_BASE) /* ADC2 Slave ADC */
#define STM32_ADC3_BASE (STM32_ADC3_OFFSET+STM32_ADC34_BASE) /* ADC3 Master ADC */
#define STM32_ADC4_BASE (STM32_ADC4_OFFSET+STM32_ADC34_BASE) /* ADC4 Slave ADC */
#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */
#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC34_BASE) /* ADC3, ADC4 common */
/* ADC1, ADC2 common - ADC2 not present on STM32 M0/M0+ devices */
#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC1_BASE)
/* Register Offsets *********************************************************/

2
arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h
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@ -99,7 +99,7 @@
#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff USART6 */
#define STM32_USART7_BASE 0x40011800 /* 0x40011800-0x40011bff USART7 */
#define STM32_USART8_BASE 0x40011c00 /* 0x40011c00-0x40011fff USART8 */
#define STM32_ADC12_BASE 0x40012400 /* 0x40012400-0x400127ff ADC 12 */
#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC1 */
#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */

2
arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h
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@ -103,7 +103,7 @@
#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff USART6 */
#define STM32_USART7_BASE 0x40011800 /* 0x40011800-0x40011bff USART7 */
#define STM32_USART8_BASE 0x40011c00 /* 0x40011c00-0x40011fff USART8 */
#define STM32_ADC12_BASE 0x40012400 /* 0x40012400-0x400127ff ADC 12 */
#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC1 */
#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */

2
arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h
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@ -86,7 +86,7 @@
#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG */
/* EXTI ??? */
#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC 1 */
#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC1 */
#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */

2
arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h
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@ -88,7 +88,7 @@
#define STM32_TIM21_BASE 0x40010800 /* 0x40010800-0x40010bff TIM21 */
#define STM32_TIM22_BASE 0x40014000 /* 0x40014000-0x400117ff TIM22 */
#define STM32_FIREWALL_BASE 0x4001c000 /* 0x4001c000-0x400113ff Firewall */
#define STM32_ADC12_BASE 0x40012400 /* 0x40012400-0x400127ff ADC12 */
#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC1 */
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */
#define STM32_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */