Mirtoo differences from Konstantin; File system fix from Lorenz Meier
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5360 42af7a65-404d-4744-a932-0658087f49c3
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@ -10,4 +10,9 @@ config ARCH_LEDS
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---help---
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"Support control of board LEDs by NuttX to indicate system state"
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config MIRTOO_RELEASE
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int "Mirtoo Release 1 (R1)"
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default 2
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---help---
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Select the Mirtoo release number
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endif
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@ -199,19 +199,19 @@ PIN PIC32 SIGNAL(s) BOARD SIGNAL/USAGE
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--- ------------------------------------------------ ---------------------------------- ----------------------------------
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29 VSS VSS Not available off module
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--- ------------------------------------------------ ---------------------------------- ----------------------------------
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30 OSC1/CLKI/RPA2/RA2 SO Not available off module
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30 OSC1/CLKI/RPA2/RA2 SO (R1) DIN0 (R2) Not available off module
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OSC1 Oscillator crystal input Not available
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CLKI External clock source input Not available
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RPRA2 Peripheral Selection PORTA, Pin 2 Used for SO
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RA2 PORTA, Pin 2 Not available
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--- ------------------------------------------------ ---------------------------------- ----------------------------------
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31 OSC2/CLKO/RPA3/RA3 DIN0 PORT0, to X1, pin 2
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31 OSC2/CLKO/RPA3/RA3 DIN0 (R1) DIN3 (R2) PORT0, to X1, pin 2
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OSC2 Oscillator crystal output Not available (also X13, pin1)
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CLKO Oscillator crystal output Not available
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RPA3 Peripheral Selection for PORTA, Pin 3 May be used for peripheral input
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RA3 PORTA, Pin 3 May be used for GPIO input
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--- ------------------------------------------------ ---------------------------------- ----------------------------------
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32 TDO/RPA8/PMA8/RA8 DIN3 PORT3, to X5, pin 2
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32 TDO/RPA8/PMA8/RA8 DIN3 (R1) S0 (R2) PORT3, to X5, pin 2
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TDO JTAG test data output pin Not available (also X13, pin7)
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RPA8 PORTA, Pin 8 May be used for peripheral input
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PMA8 Parallel Master Port Address bit 8 Not available
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@ -74,7 +74,8 @@
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* PIN SIGNAL BOARD CONNECTION NOTES
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* ------ -------- ------------------------- --------------------------------
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* RPA1 SI PGA117 and SST25VF032B SPI2 data OUT (SDO2)
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* RPA2 SO PGA117 and SST25VF032B SPI2 data IN (SDI2)
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* RPA2 SO PGA117 and SST25VF032B R1, SPI2 data IN (SDI2)
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* RPA3 SO PGA117 and SST25VF032B R0, SPI2 data IN (SDI2)
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* SCK2 SCK PGA117 and SST25VF032B SPI2 clock
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*
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* RB7 ~CSAI PGA117 PGA117 chip select (active low)
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@ -82,8 +83,12 @@
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*/
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#define GPIO_SI (GPIO_OUTPUT|GPIO_PORTA|GPIO_PIN1)
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#define GPIO_SO (GPIO_INPUT|GPIO_PORTA|GPIO_PIN1)
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#define GPIO_SCK (GPIO_OUTPUT|GPIO_PORTA|GPIO_PIN1)
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#ifdef CONFIG_MIRTOO_RELEASE == 1
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# define GPIO_SO (GPIO_INPUT|GPIO_PORTA|GPIO_PIN2)
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#else
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# define GPIO_SO (GPIO_INPUT|GPIO_PORTA|GPIO_PIN3)
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#endif
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#define GPIO_SCK (GPIO_OUTPUT|GPIO_PORTB|GPIO_PIN15)
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#define GPIO_PGA117_CS (GPIO_OUTPUT|GPIO_VALUE_ONE|GPIO_PORTB|GPIO_PIN7)
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#define GPIO_SST25VF032B_CS (GPIO_OUTPUT|GPIO_VALUE_ONE|GPIO_PORTB|GPIO_PIN13)
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