From 43b7d9b0da1c4141d2813aed53f4eeeea4e2f04a Mon Sep 17 00:00:00 2001 From: Gustavo Henrique Nihei Date: Fri, 18 Mar 2022 09:26:05 -0300 Subject: [PATCH] xtensa/esp32s3: Sync GPIO sigmap with IDF version Signed-off-by: Gustavo Henrique Nihei --- .../esp32s3/hardware/esp32s3_gpio_sigmap.h | 47 ++++++++++++++----- 1 file changed, 35 insertions(+), 12 deletions(-) diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_gpio_sigmap.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_gpio_sigmap.h index 5c59d55d54..dc403331a1 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_gpio_sigmap.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_gpio_sigmap.h @@ -22,8 +22,9 @@ #define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_GPIO_SIGMAP_H /**************************************************************************** - * Included Files + * Pre-processor Definitions ****************************************************************************/ + #define SPIQ_IN_IDX 0 #define SPIQ_OUT_IDX 0 #define SPID_IN_IDX 1 @@ -129,7 +130,8 @@ #define BB_DIAG17_IDX 52 #define I2S0I_SD3_IN_IDX 53 #define BB_DIAG18_IDX 53 -#define BB_DIAG19_IDX 54 +#define CORE1_GPIO_IN7_IDX 54 +#define CORE1_GPIO_OUT7_IDX 54 #define USB_EXTPHY_VP_IDX 55 #define USB_EXTPHY_OEN_IDX 55 #define USB_EXTPHY_VM_IDX 56 @@ -179,6 +181,10 @@ #define RMT_SIG_OUT2_IDX 83 #define RMT_SIG_IN3_IDX 84 #define RMT_SIG_OUT3_IDX 84 +#define USB_JTAG_TCK_IDX 85 +#define USB_JTAG_TMS_IDX 86 +#define USB_JTAG_TDI_IDX 87 +#define USB_JTAG_TDO_IDX 88 #define I2CEXT0_SCL_IN_IDX 89 #define I2CEXT0_SCL_OUT_IDX 89 #define I2CEXT0_SDA_IN_IDX 90 @@ -237,6 +243,13 @@ #define SUBSPICS1_OUT_IDX 125 #define FSPIDQS_OUT_IDX 126 #define SPI3_CS2_OUT_IDX 127 +#define I2S0O_SD1_OUT_IDX 128 +#define CORE1_GPIO_IN0_IDX 129 +#define CORE1_GPIO_OUT0_IDX 129 +#define CORE1_GPIO_IN1_IDX 130 +#define CORE1_GPIO_OUT1_IDX 130 +#define CORE1_GPIO_IN2_IDX 131 +#define CORE1_GPIO_OUT2_IDX 131 #define LCD_CS_IDX 132 #define CAM_DATA_IN0_IDX 133 #define LCD_DATA_OUT0_IDX 133 @@ -378,16 +391,16 @@ #define ANT_SEL5_IDX 205 #define ANT_SEL6_IDX 206 #define ANT_SEL7_IDX 207 -#define SIG_IN_FUNC_223_IDX 208 -#define SIG_IN_FUNC223_IDX 208 -#define SIG_IN_FUNC_224_IDX 209 -#define SIG_IN_FUNC224_IDX 209 -#define SIG_IN_FUNC_225_IDX 210 -#define SIG_IN_FUNC225_IDX 210 -#define SIG_IN_FUNC_226_IDX 211 -#define SIG_IN_FUNC226_IDX 211 -#define SIG_IN_FUNC_227_IDX 212 -#define SIG_IN_FUNC227_IDX 212 +#define SIG_IN_FUNC_208_IDX 208 +#define SIG_IN_FUNC208_IDX 208 +#define SIG_IN_FUNC_209_IDX 209 +#define SIG_IN_FUNC209_IDX 209 +#define SIG_IN_FUNC_210_IDX 210 +#define SIG_IN_FUNC210_IDX 210 +#define SIG_IN_FUNC_211_IDX 211 +#define SIG_IN_FUNC211_IDX 211 +#define SIG_IN_FUNC_212_IDX 212 +#define SIG_IN_FUNC212_IDX 212 #define SDHOST_CDATA_IN_20_IDX 213 #define SDHOST_CDATA_OUT_20_IDX 213 #define SDHOST_CDATA_IN_21_IDX 214 @@ -442,6 +455,16 @@ #define RX_STATUS_IDX 248 #define CLK_GPIO_IDX 249 #define NBT_BLE_IDX 250 +#define USB_JTAG_TDO_BRIDGE_IDX 251 +#define USB_JTAG_TRST_IDX 251 +#define CORE1_GPIO_IN3_IDX 252 +#define CORE1_GPIO_OUT3_IDX 252 +#define CORE1_GPIO_IN4_IDX 253 +#define CORE1_GPIO_OUT4_IDX 253 +#define CORE1_GPIO_IN5_IDX 254 +#define CORE1_GPIO_OUT5_IDX 254 +#define CORE1_GPIO_IN6_IDX 255 +#define CORE1_GPIO_OUT6_IDX 255 #define SIG_GPIO_OUT_IDX 256 #endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_GPIO_SIGMAP_H */