From 42720a54733fcd191b34c76b922e29749e11ba44 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 7 Feb 2018 14:55:56 -0600 Subject: [PATCH] Update README --- configs/sabre-6quad/README.txt | 119 ++++++++++++++++++++++++++++++--- 1 file changed, 108 insertions(+), 11 deletions(-) diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index 331867888d..f16dc76113 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -152,9 +152,9 @@ Status minimum amount of time. With these changes, basic SMP functionality is restored and there are no - known issues (Configuration smp with 4 CPUs and data cache disabled). It - is likely, however, that additional changes similar to the above will be - required in other areas of the OS, but none such are known as of this + known issues (Configuration 'smp' with 4 CPUs and data cache disabled). + It is possible, however, that additional changes similar to the above will + be required in other areas of the OS, but none such are known as of this writing. Insufficient stress testing has been done to prove that the solution is stable. @@ -625,11 +625,6 @@ index eedf179..1db2092 100644 SMP support. There are no known problem but the changes have not been verified fully (see STATUS above for 2019-02-06). -4. I have a sense that there may be some performance issues that need to be worked - out. I have made no measurements so perhaps that is an unfounded concern but - you should be aware even of my unfounded concerns if you want to work with i.MX6 - SMP. - Configurations ============== @@ -720,12 +715,114 @@ Configuration sub-directories smp --- This is a configuration of testing the SMP configuration. It is - essentially equivalent to the SMP configuration except has SMP enabled. + essentially equivalent to the nsh configuration except has SMP enabled + and supports apps/examples/smp. + + Sample output of the SMP test is show below (Configuration all 4 CPUs + but with data cache disabled): + + NuttShell (NSH) NuttX-7.23 + nsh> smp + Main[0]: Running on CPU0 + Main[0]: Initializing barrier + Thread[1]: Started + Main[0]: Thread 1 created + Thread[1]: Running on CPU0 + Main[0]: Now running on CPU1 + Thread[2]: Started + Main[0]: Thread 2 created + Thread[2]: Running on CPU1 + Main[0]: Now running on CPU2 + Thread[3]: Started + Main[0]: Thread 3 created + Thread[3]: Running on CPU2 + Main[0]: Now running on CPU3 + Thread[4]: Started + Thread[4]: Running on CPU3 + Main[0]: Thread 4 created + Main[0]: Now running on CPU0 + Thread[5]: Started + Thread[5]: Running on CPU0 + Main[0]: Thread 5 created + Thread[6]: Started + Thread[6]: Running on CPU0 + Main[0]: Thread 6 created + Thread[7]: Started + Thread[7]: Running on CPU0 + Main[0]: Thread 7 created + Thread[8]: Started + Thread[8]: Running on CPU0 + Main[0]: Thread 8 created + Thread[2]: Now running on CPU0 + Thread[3]: Now running on CPU0 + Thread[4]: Now running on CPU0 + Thread[3]: Now running on CPU2 + Thread[3]: Now running on CPU0 + Thread[5]: Now running on CPU1 + Thread[5]: Now running on CPU0 + Thread[6]: Calling pthread_barrier_wait() + Thread[8]: Calling pthread_barrier_wait() + Thread[3]: Calling pthread_barrier_wait() + Thread[5]: Calling pthread_barrier_wait() + Thread[1]: Calling pthread_barrier_wait() + Thread[2]: Now running on CPU2 + Thread[2]: Calling pthread_barrier_wait() + Thread[7]: Now running on CPU3 + Thread[4]: Now running on CPU1 + Thread[4]: Calling pthread_barrier_wait() + Thread[7]: Calling pthread_barrier_wait() + Thread[7]: Back with ret=PTHREAD_BARRIER_SERIAL_THREAD (I AM SPECIAL) + Thread[6]: Back with ret=0 (I am not special) + Thread[8]: Back with ret=0 (I am not special) + Thread[3]: Back with ret=0 (I am not special) + Thread[5]: Back with ret=0 (I am not special) + Thread[1]: Back with ret=0 (I am not special) + Thread[2]: Back with ret=0 (I am not special) + Thread[4]: Back with ret=0 (I am not special) + Thread[7]: Now running on CPU1 + Thread[6]: Now running on CPU2 + Thread[3]: Now running on CPU1 + Thread[5]: Now running on CPU2 + Thread[1]: Now running on CPU1 + Thread[4]: Now running on CPU3 + Thread[2]: Now running on CPU0 + Thread[7]: Now running on CPU0 + Thread[6]: Now running on CPU0 + Thread[3]: Now running on CPU0 + Thread[4]: Now running on CPU0 + Thread[1]: Now running on CPU0 + Thread[5]: Now running on CPU0 + Thread[3]: Now running on CPU3 + Thread[3]: Now running on CPU0 + Thread[4]: Now running on CPU2 + Thread[3]: Done + Thread[4]: Now running on CPU0 + Thread[4]: Done + Thread[7]: Done + Thread[2]: Done + Thread[5]: Now running on CPU2 + Thread[8]: Now running on CPU1 + Thread[8]: Done + Thread[6]: Now running on CPU3 + Thread[5]: Done + Thread[1]: Done + Main[0]: Now running on CPU1 + Main[0]: Thread 1 completed with result=0 + Main[0]: Thread 2 completed with result=0 + Main[0]: Thread 3 completed with result=0 + Main[0]: Thread 4 completed with result=0 + Main[0]: Thread 5 completed with result=0 + Thread[6]: Done + Main[0]: Now running on CPU0 + Main[0]: Thread 6 completed with result=0 + Main[0]: Thread 7 completed with result=0 + Main[0]: Thread 8 completed with result=0 + nsh> NOTES: 1. See the notes for the nsh configuration. Since this configuration is essentially the same all of those comments apply. - 2. SMP is not fully functional. See the STATUS and SMP sections above - for detailed SMP-related issues. + 2. See the STATUS and SMP sections above for detailed SMP-related + issues.