imxrt:Ethernet Add LAN8742A support
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@ -125,6 +125,12 @@
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# error Write back D-Cache not yet supported
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# error Write back D-Cache not yet supported
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#endif
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#endif
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/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
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* second.
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*/
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#define IMXRT_WDDELAY (1 * CLK_TCK)
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/* Align assuming that the D-Cache is enabled (probably 32-bytes).
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/* Align assuming that the D-Cache is enabled (probably 32-bytes).
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*
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*
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* REVISIT: The size of descriptors and buffers must also be in even units
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* REVISIT: The size of descriptors and buffers must also be in even units
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@ -191,6 +197,15 @@
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# define BOARD_PHY_10BASET(s) (((s)&MII_LAN8720_SPSCR_10MBPS) != 0)
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# define BOARD_PHY_10BASET(s) (((s)&MII_LAN8720_SPSCR_10MBPS) != 0)
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# define BOARD_PHY_100BASET(s) (((s)&MII_LAN8720_SPSCR_100MBPS) != 0)
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# define BOARD_PHY_100BASET(s) (((s)&MII_LAN8720_SPSCR_100MBPS) != 0)
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# define BOARD_PHY_ISDUPLEX(s) (((s)&MII_LAN8720_SPSCR_DUPLEX) != 0)
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# define BOARD_PHY_ISDUPLEX(s) (((s)&MII_LAN8720_SPSCR_DUPLEX) != 0)
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#elif defined(CONFIG_ETH0_PHY_LAN8742A)
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# define BOARD_PHY_NAME "LAN8742A"
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# define BOARD_PHYID1 MII_PHYID1_LAN8742A
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# define BOARD_PHYID2 MII_PHYID2_LAN8742A
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# define BOARD_PHY_STATUS MII_LAN8740_SCSR
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# define BOARD_PHY_ADDR (0)
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# define BOARD_PHY_10BASET(s) (((s)&MII_LAN8720_SPSCR_10MBPS) != 0)
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# define BOARD_PHY_100BASET(s) (((s)&MII_LAN8720_SPSCR_100MBPS) != 0)
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# define BOARD_PHY_ISDUPLEX(s) (((s)&MII_LAN8720_SPSCR_DUPLEX) != 0)
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#elif defined(CONFIG_ETH0_PHY_DP83825I)
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#elif defined(CONFIG_ETH0_PHY_DP83825I)
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# define BOARD_PHY_NAME "DP83825I"
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# define BOARD_PHY_NAME "DP83825I"
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# define BOARD_PHYID1 MII_PHYID1_DP83825I
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# define BOARD_PHYID1 MII_PHYID1_DP83825I
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@ -2071,7 +2086,7 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)
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MII_ADVERTISE_10BASETXHALF |
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MII_ADVERTISE_10BASETXHALF |
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MII_ADVERTISE_CSMA);
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MII_ADVERTISE_CSMA);
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#elif defined (CONFIG_ETH0_PHY_LAN8720)
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#elif defined (CONFIG_ETH0_PHY_LAN8720) || defined (CONFIG_ETH0_PHY_LAN8742A)
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/* Make sure that PHY comes up in correct mode when it's reset */
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/* Make sure that PHY comes up in correct mode when it's reset */
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imxrt_writemii(priv, phyaddr, MII_LAN8720_MODES,
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imxrt_writemii(priv, phyaddr, MII_LAN8720_MODES,
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