arch/arm/src/stm32h7: Port QSPI driver from STM32F7 to STM32H7
This commit is contained in:
Minamiya_Natsuki
Gregory Nutt
parent
7136215930
commit
390ebd504f
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@ -236,6 +236,4 @@
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32L4_QSPI_H */
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#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F7_QSPI_H */
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@ -304,6 +304,10 @@ config STM32H7_OTG_USBREGEN
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bool "Enable USB voltage regulator"
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default n
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config STM32H7_QUADSPI
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bool "QuadSPI"
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default n
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config STM32H7_USBDEV_REGDEBUG
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bool "OTG USBDEV REGDEBUG"
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default n
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@ -1154,6 +1158,8 @@ config STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
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endif # STM32H7_RTC_LSECLOCK
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endmenu # RTC Configuration
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config STM32H7_EXTERNAL_RAM
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bool "External RAM on FMC"
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default n
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@ -1162,7 +1168,139 @@ config STM32H7_EXTERNAL_RAM
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---help---
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In addition to internal SDRAM, external RAM may be available through the FMC.
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endmenu # RTC Configuration
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menu "QuadSPI Configuration"
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depends on STM32H7_QUADSPI
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config STM32H7_QSPI_FLASH_SIZE
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int "Size of attached serial flash, bytes"
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default 16777216
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range 1 2147483648
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---help---
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The STM32H7 QSPI peripheral requires the size of the Flash be specified
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config STM32H7_QSPI_FIFO_THESHOLD
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int "Number of bytes before asserting FIFO threshold flag"
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default 4
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range 1 16
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---help---
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The STM32H7 QSPI peripheral requires that the FIFO threshold be specified
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I would leave it at the default value of 4 unless you know what you are doing.
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config STM32H7_QSPI_CSHT
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int "Number of cycles Chip Select must be inactive between transactions"
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default 1
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range 1 8
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---help---
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The STM32H7 QSPI peripheral requires that it be specified the minimum number
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of AHB cycles that Chip Select be held inactive between transactions.
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choice
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prompt "Transfer technique"
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default STM32H7_QSPI_DMA
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---help---
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You can choose between using polling, interrupts, or DMA to transfer data
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over the QSPI interface.
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config STM32H7_QSPI_POLLING
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bool "Polling"
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---help---
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Use conventional register I/O with status polling to transfer data.
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config STM32H7_QSPI_INTERRUPTS
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bool "Interrupts"
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---help---
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User interrupt driven I/O transfers.
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config STM32H7_QSPI_DMA
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bool "DMA"
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depends on STM32H7_DMA
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---help---
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Use DMA to improve QSPI transfer performance.
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endchoice
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choice
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prompt "Bank selection"
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default STM32H7_QSPI_MODE_BANK1
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---help---
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You can choose between using polling, interrupts, or DMA to transfer data
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over the QSPI interface.
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config STM32H7_QSPI_MODE_BANK1
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bool "Bank 1"
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config STM32H7_QSPI_MODE_BANK2
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bool "Bank 2"
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config STM32H7_QSPI_MODE_DUAL
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bool "Dual Bank"
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endchoice
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choice
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prompt "DMA Priority"
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default STM32H7_QSPI_DMAPRIORITY_MEDIUM
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depends on STM32H7_DMA
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---help---
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The DMA controller supports priority levels. You are probably fine
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with the default of 'medium' except for special cases. In the event
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of contention between to channels at the same priority, the lower
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numbered channel has hardware priority over the higher numbered one.
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config STM32H7_QSPI_DMAPRIORITY_VERYHIGH
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bool "Very High priority"
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depends on STM32H7_DMA
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---help---
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'Highest' priority.
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config STM32H7_QSPI_DMAPRIORITY_HIGH
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bool "High priority"
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depends on STM32H7_DMA
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---help---
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'High' priority.
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config STM32H7_QSPI_DMAPRIORITY_MEDIUM
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bool "Medium priority"
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depends on STM32H7_DMA
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---help---
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'Medium' priority.
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config STM32H7_QSPI_DMAPRIORITY_LOW
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bool "Low priority"
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depends on STM32H7_DMA
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---help---
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'Low' priority.
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endchoice
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config STM32H7_QSPI_DMATHRESHOLD
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int "QSPI DMA threshold"
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default 4
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depends on STM32H7_QSPI_DMA
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---help---
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When QSPI DMA is enabled, small DMA transfers will still be performed
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by polling logic. This value is the threshold below which transfers
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will still be performed by conventional register status polling.
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config STM32H7_QSPI_DMADEBUG
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bool "QSPI DMA transfer debug"
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depends on STM32H7_QSPI_DMA && DEBUG_SPI && DEBUG_DMA
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default n
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---help---
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Enable special debug instrumentation to analyze QSPI DMA data transfers.
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This logic is as non-invasive as possible: It samples DMA
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registers at key points in the data transfer and then dumps all of
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the registers at the end of the transfer.
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config STM32H7_QSPI_REGDEBUG
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bool "QSPI Register level debug"
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depends on DEBUG_SPI_INFO
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default n
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---help---
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Output detailed register-level QSPI device debug information.
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Requires also CONFIG_DEBUG_SPI_INFO.
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endmenu
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config STM32H7_CUSTOM_CLOCKCONFIG
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bool "Custom clock configuration"
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@ -161,6 +161,11 @@ ifeq ($(CONFIG_STM32H7_PWR),y)
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CHIP_CSRCS += stm32_pwr.c
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endif
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ifeq ($(CONFIG_STM32H7_QUADSPI),y)
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CHIP_CSRCS += stm32_qspi.c
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endif
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ifeq ($(CONFIG_STM32H7_RTC),y)
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CHIP_CSRCS += stm32_rtc.c
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ifeq ($(CONFIG_RTC_ALARM),y)
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@ -0,0 +1,239 @@
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/****************************************************************************
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* arch/arm/src/stm32h7/hardware/stm32_qspi.h
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*
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* Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
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* Author: dev@ziggurat29.com
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7_QSPI_H
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#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7_QSPI_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/stm32h7/chip.h>
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#include "chip.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* General Characteristics **************************************************************/
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#define STM32H7_QSPI_MINBITS 8 /* Minimum word width */
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#define STM32H7_QSPI_MAXBITS 32 /* Maximum word width */
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/* QSPI register offsets ****************************************************************/
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#define STM32_QUADSPI_CR_OFFSET 0x0000 /* Control Register */
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#define STM32_QUADSPI_DCR_OFFSET 0x0004 /* Device Configuration Register */
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#define STM32_QUADSPI_SR_OFFSET 0x0008 /* Status Register */
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#define STM32_QUADSPI_FCR_OFFSET 0x000c /* Flag Clear Register */
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#define STM32_QUADSPI_DLR_OFFSET 0x0010 /* Data Length Register */
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#define STM32_QUADSPI_CCR_OFFSET 0x0014 /* Communication Configuration Register */
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#define STM32_QUADSPI_AR_OFFSET 0x0018 /* Address Register */
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#define STM32_QUADSPI_ABR_OFFSET 0x001c /* Alternate Bytes Register */
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#define STM32_QUADSPI_DR_OFFSET 0x0020 /* Data Register */
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#define STM32_QUADSPI_PSMKR_OFFSET 0x0024 /* Polling Status mask Register */
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#define STM32_QUADSPI_PSMAR_OFFSET 0x0028 /* Polling Status match Register */
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#define STM32_QUADSPI_PIR_OFFSET 0x002c /* Polling Interval Register */
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#define STM32_QUADSPI_LPTR_OFFSET 0x0030 /* Low-Power Timeout Register */
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/* QSPI register addresses **************************************************************/
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#define STM32_QUADSPI_CR (STM32_QUADSPI_BASE+STM32_QUADSPI_CR_OFFSET) /* Control Register */
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#define STM32_QUADSPI_DCR (STM32_QUADSPI_BASE+STM32_QUADSPI_DCR_OFFSET) /* Device Configuration Register */
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#define STM32_QUADSPI_SR (STM32_QUADSPI_BASE+STM32_QUADSPI_SR_OFFSET) /* Status Register */
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#define STM32_QUADSPI_FCR (STM32_QUADSPI_BASE+STM32_QUADSPI_FCR_OFFSET) /* Flag Clear Register */
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#define STM32_QUADSPI_DLR (STM32_QUADSPI_BASE+STM32_QUADSPI_DLR_OFFSET) /* Data Length Register */
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#define STM32_QUADSPI_CCR (STM32_QUADSPI_BASE+STM32_QUADSPI_CCR_OFFSET) /* Communication Configuration Register */
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#define STM32_QUADSPI_AR (STM32_QUADSPI_BASE+STM32_QUADSPI_AR_OFFSET) /* Address Register */
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#define STM32_QUADSPI_ABR (STM32_QUADSPI_BASE+STM32_QUADSPI_ABR_OFFSET) /* Alternate Bytes Register */
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#define STM32_QUADSPI_DR (STM32_QUADSPI_BASE+STM32_QUADSPI_DR_OFFSET) /* Data Register */
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#define STM32_QUADSPI_PSMKR (STM32_QUADSPI_BASE+STM32_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */
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#define STM32_QUADSPI_PSMAR (STM32_QUADSPI_BASE+STM32_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */
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#define STM32_QUADSPI_PIR (STM32_QUADSPI_BASE+STM32_QUADSPI_PIR_OFFSET) /* Polling Interval Register */
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#define STM32_QUADSPI_LPTR (STM32_QUADSPI_BASE+STM32_QUADSPI_LPTR_OFFSET) /* Low-Power Timeout Register */
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/* QSPI register bit definitions ********************************************************/
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/* Control Register */
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#define QSPI_CR_EN (1 << 0) /* Bit 0: QSPI Enable */
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#define QSPI_CR_ABORT (1 << 1) /* Bit 1: Abort request */
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#define QSPI_CR_TCEN (1 << 3) /* Bit 3: Timeout counter enable */
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#define QSPI_CR_SSHIFT (1 << 4) /* Bit 4: Sample shift */
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#define QSPI_CR_DFM (1 << 6) /* Bit 6: DFM: Dual-flash mode */
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#define QSPI_CR_FSEL (1 << 7) /* Bit 7: FSEL: Flash memory selection */
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#define QSPI_CR_FTHRES_SHIFT (8) /* Bits 8-11: FIFO threshold level */
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#define QSPI_CR_FTHRES_MASK (0x0f << QSPI_CR_FTHRES_SHIFT)
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#define QSPI_CR_TEIE (1 << 16) /* Bit 16: Transfer error interrupt enable */
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#define QSPI_CR_TCIE (1 << 17) /* Bit 17: Transfer complete interrupt enable */
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#define QSPI_CR_FTIE (1 << 18) /* Bit 18: FIFO threshold interrupt enable */
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#define QSPI_CR_SMIE (1 << 19) /* Bit 19: Status match interrupt enable */
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#define QSPI_CR_TOIE (1 << 20) /* Bit 20: TimeOut interrupt enable */
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#define QSPI_CR_APMS (1 << 22) /* Bit 22: Automatic poll mode stop */
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#define QSPI_CR_PMM (1 << 23) /* Bit 23: Polling match mode */
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#define QSPI_CR_PRESCALER_SHIFT (24) /* Bits 24-31: Clock prescaler */
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#define QSPI_CR_PRESCALER_MASK (0xff << QSPI_CR_PRESCALER_SHIFT)
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/* Device Configuration Register */
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#define QSPI_DCR_CKMODE (1 << 0) /* Bit 0: Mode 0 / mode 3 */
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#define QSPI_DCR_CSHT_SHIFT (8) /* Bits 8-10: Chip select high time */
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#define QSPI_DCR_CSHT_MASK (0x7 << QSPI_DCR_CSHT_SHIFT)
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#define QSPI_DCR_FSIZE_SHIFT (16) /* Bits 16-20: Flash memory size */
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#define QSPI_DCR_FSIZE_MASK (0x1f << QSPI_DCR_FSIZE_SHIFT)
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/* Status Register */
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#define QSPI_SR_TEF (1 << 0) /* Bit 0: Transfer error flag */
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#define QSPI_SR_TCF (1 << 1) /* Bit 1: Transfer complete flag */
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#define QSPI_SR_FTF (1 << 2) /* Bit 2: FIFO threshold flag */
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#define QSPI_SR_SMF (1 << 3) /* Bit 3: Status match flag */
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#define QSPI_SR_TOF (1 << 4) /* Bit 4: Timeout flag */
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#define QSPI_SR_BUSY (1 << 5) /* Bit 5: Busy */
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#define QSPI_SR_FLEVEL_SHIFT (8) /* Bits 8-12: FIFO threshold level */
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#define QSPI_SR_FLEVEL_MASK (0x1f << QSPI_SR_FLEVEL_SHIFT)
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/* Flag Clear Register */
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#define QSPI_FCR_CTEF (1 << 0) /* Bit 0: Clear Transfer error flag */
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#define QSPI_FCR_CTCF (1 << 1) /* Bit 1: Clear Transfer complete flag */
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#define QSPI_FCR_CSMF (1 << 3) /* Bit 3: Clear Status match flag */
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#define QSPI_FCR_CTOF (1 << 4) /* Bit 4: Clear Timeout flag */
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/* Data Length Register */
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/* Communication Configuration Register */
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#define CCR_IMODE_NONE 0 /* No instruction */
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#define CCR_IMODE_SINGLE 1 /* Instruction on a single line */
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#define CCR_IMODE_DUAL 2 /* Instruction on two lines */
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#define CCR_IMODE_QUAD 3 /* Instruction on four lines */
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#define CCR_ADMODE_NONE 0 /* No address */
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#define CCR_ADMODE_SINGLE 1 /* Address on a single line */
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#define CCR_ADMODE_DUAL 2 /* Address on two lines */
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#define CCR_ADMODE_QUAD 3 /* Address on four lines */
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#define CCR_ADSIZE_8 0 /* 8-bit address */
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#define CCR_ADSIZE_16 1 /* 16-bit address */
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#define CCR_ADSIZE_24 2 /* 24-bit address */
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#define CCR_ADSIZE_32 3 /* 32-bit address */
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#define CCR_ABMODE_NONE 0 /* No alternate bytes */
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#define CCR_ABMODE_SINGLE 1 /* Alternate bytes on a single line */
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#define CCR_ABMODE_DUAL 2 /* Alternate bytes on two lines */
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#define CCR_ABMODE_QUAD 3 /* Alternate bytes on four lines */
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#define CCR_ABSIZE_8 0 /* 8-bit alternate byte */
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#define CCR_ABSIZE_16 1 /* 16-bit alternate bytes */
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#define CCR_ABSIZE_24 2 /* 24-bit alternate bytes */
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#define CCR_ABSIZE_32 3 /* 32-bit alternate bytes */
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#define CCR_DMODE_NONE 0 /* No data */
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#define CCR_DMODE_SINGLE 1 /* Data on a single line */
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#define CCR_DMODE_DUAL 2 /* Data on two lines */
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#define CCR_DMODE_QUAD 3 /* Data on four lines */
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#define CCR_FMODE_INDWR 0 /* Indirect write mode */
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#define CCR_FMODE_INDRD 1 /* Indirect read mode */
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#define CCR_FMODE_AUTOPOLL 2 /* Automatic polling mode */
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#define CCR_FMODE_MEMMAP 3 /* Memory-mapped mode */
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#define QSPI_CCR_INSTRUCTION_SHIFT (0) /* Bits 0-7: Instruction */
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#define QSPI_CCR_INSTRUCTION_MASK (0xff << QSPI_CCR_INSTRUCTION_SHIFT)
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# define QSPI_CCR_INST(n) ((uint32_t)(n) << QSPI_CCR_INSTRUCTION_SHIFT)
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#define QSPI_CCR_IMODE_SHIFT (8) /* Bits 8-9: Instruction mode */
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#define QSPI_CCR_IMODE_MASK (0x3 << QSPI_CCR_IMODE_SHIFT)
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# define QSPI_CCR_IMODE(n) ((uint32_t)(n) << QSPI_CCR_IMODE_SHIFT)
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#define QSPI_CCR_ADMODE_SHIFT (10) /* Bits 10-11: Address mode */
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#define QSPI_CCR_ADMODE_MASK (0x3 << QSPI_CCR_ADMODE_SHIFT)
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# define QSPI_CCR_ADMODE(n) ((uint32_t)(n) << QSPI_CCR_ADMODE_SHIFT)
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#define QSPI_CCR_ADSIZE_SHIFT (12) /* Bits 12-13: Address size */
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#define QSPI_CCR_ADSIZE_MASK (0x3 << QSPI_CCR_ADSIZE_SHIFT)
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# define QSPI_CCR_ADSIZE(n) ((uint32_t)(n) << QSPI_CCR_ADSIZE_SHIFT)
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#define QSPI_CCR_ABMODE_SHIFT (14) /* Bits 14-15: Alternate bytes mode */
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#define QSPI_CCR_ABMODE_MASK (0x3 << QSPI_CCR_ABMODE_SHIFT)
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# define QSPI_CCR_ABMODE(n) ((uint32_t)(n) << QSPI_CCR_ABMODE_SHIFT)
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#define QSPI_CCR_ABSIZE_SHIFT (16) /* Bits 16-17: Alternate bytes size */
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#define QSPI_CCR_ABSIZE_MASK (0x3 << QSPI_CCR_ABSIZE_SHIFT)
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# define QSPI_CCR_ABSIZE(n) ((uint32_t)(n) << QSPI_CCR_ABSIZE_SHIFT)
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#define QSPI_CCR_DCYC_SHIFT (18) /* Bits 18-23: Number of dummy cycles */
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#define QSPI_CCR_DCYC_MASK (0x1f << QSPI_CCR_DCYC_SHIFT)
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# define QSPI_CCR_DCYC(n) ((uint32_t)(n) << QSPI_CCR_DCYC_SHIFT)
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#define QSPI_CCR_DMODE_SHIFT (24) /* Bits 24-25: Data mode */
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#define QSPI_CCR_DMODE_MASK (0x3 << QSPI_CCR_DMODE_SHIFT)
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# define QSPI_CCR_DMODE(n) ((uint32_t)(n) << QSPI_CCR_DMODE_SHIFT)
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#define QSPI_CCR_FMODE_SHIFT (26) /* Bits 26-27: Functional mode */
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#define QSPI_CCR_FMODE_MASK (0x3 << QSPI_CCR_FMODE_SHIFT)
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# define QSPI_CCR_FMODE(n) ((uint32_t)(n) << QSPI_CCR_FMODE_SHIFT)
|
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#define QSPI_CCR_SIOO (1 << 28) /* Bit 28: Send instruction only once mode */
|
||||
#define QSPI_CCR_FRCM (1 << 29) /* Bit 28: Enters Free running clock mode */
|
||||
#define QSPI_CCR_DDRM (1 << 31) /* Bit 31: Double data rate mode */
|
||||
|
||||
/* Address Register */
|
||||
|
||||
/* Alternate Bytes Register */
|
||||
|
||||
/* Data Register */
|
||||
|
||||
/* Polling Status mask Register */
|
||||
|
||||
/* Polling Status match Register */
|
||||
|
||||
/* Polling Interval Register */
|
||||
|
||||
#define QSPI_PIR_INTERVAL_SHIFT (0) /* Bits 0-15: Polling interval */
|
||||
#define QSPI_PIR_INTERVAL_MASK (0xFFff << QSPI_PIR_INTERVAL_SHIFT)
|
||||
|
||||
/* Low-Power Timeout Register */
|
||||
|
||||
#define QSPI_LPTR_TIMEOUT_SHIFT (0) /* Bits 0-15: Timeout period */
|
||||
#define QSPI_LPTR_TIMEOUT_MASK (0xFFff << QSPI_PIR_INTERVAL_SHIFT)
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H4_QSPI_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,144 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32h7/stm32_qspi.h
|
||||
*
|
||||
* Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: dev@ziggurat29.com
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32H7_QSPI_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32H7_QSPI_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/spi/qspi.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#ifdef CONFIG_STM32H7_QUADSPI
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_qspi_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected QSPI port in master mode
|
||||
*
|
||||
* Input Parameters:
|
||||
* intf - Interface number(must be zero)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct qspi_dev_s;
|
||||
FAR struct qspi_dev_s *stm32h7_qspi_initialize(int intf);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_qspi_enter_memorymapped
|
||||
*
|
||||
* Description:
|
||||
* Put the QSPI device into memory mapped mode
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - QSPI device
|
||||
* meminfo - parameters like for a memory transfer used for reading
|
||||
* lpto - number of cycles to wait to automatically de-assert CS
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev,
|
||||
const struct qspi_meminfo_s *meminfo,
|
||||
uint32_t lpto);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_qspi_exit_memorymapped
|
||||
*
|
||||
* Description:
|
||||
* Take the QSPI device out of memory mapped mode
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - QSPI device
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h7_qspi_exit_memorymapped(struct qspi_dev_s *dev);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_STM32H7_QSPI */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32H7_QSPI_H */
|
||||
Loading…
Reference in New Issue