More USB definitions
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3034 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -48,6 +48,8 @@
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/* Register offsets *****************************************************************/
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/* USB Device Registers */
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#define AVR32_USBB_UDCON_OFFSET 0x0000 /* Device General Control Register */
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#define AVR32_USBB_UDINT_OFFSET 0x0004 /* Device Global Interrupt Register */
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#define AVR32_USBB_UDINTCLR_OFFSET 0x0008 /* Device Global Interrupt Clear Register */
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@ -162,6 +164,8 @@
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#define AVR32_UDDMA6_CONTROL_OFFSET 0x0368 /* Device DMA Channel 6 Control Register */
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#define AVR32_UDDMA6_STATUS_OFFSET 0x036c /* Device DMA Channel 6 Status Register */
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/* USB Host Registers */
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#define AVR32_USBB_UHCON_OFFSET 0x0400 /* Host General Control Register */
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#define AVR32_USBB_UHINT_OFFSET 0x0404 /* Host Global Interrupt Register */
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#define AVR32_USBB_UHINTCLR_OFFSET 0x0408 /* Host Global Interrupt Clear Register */
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@ -291,6 +295,8 @@
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#define AVR32_UHDMA6_CONTROL_OFFSET 0x0768 /* Host DMA Channel 6 Control Register */
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#define AVR32_UHDMA6_STATUS_OFFSET 0x076c /* Host DMA Channel 6 Status Register */
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/* USB General Registers */
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#define AVR32_USBB_USBCON_OFFSET 0x0800 /* General Control Register */
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#define AVR32_USBB_USBSTA_OFFSET 0x0804 /* General Status Register */
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#define AVR32_USBB_USBSTACLR_OFFSET 0x0808 /* General Status Clear Register */
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@ -304,6 +310,8 @@
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/* Register Addresses ***************************************************************/
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/* USB Device Registers */
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#define AVR32_USBB_UDCON (AVR32_USB_BASE+AVR32_USBB_UDCON_OFFSET)
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#define AVR32_USBB_UDINT (AVR32_USB_BASE+AVR32_USBB_UDINT_OFFSET)
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#define AVR32_USBB_UDINTCLR (AVR32_USB_BASE+AVR32_USBB_UDINTCLR_OFFSET)
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@ -413,6 +421,8 @@
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#define AVR32_UDDMA6_CONTROL (AVR32_USB_BASE+AVR32_UDDMA6_CONTROL_OFFSET)
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#define AVR32_UDDMA6_STATUS (AVR32_USB_BASE+AVR32_UDDMA6_STATUS_OFFSET)
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/* USB Host Registers */
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#define AVR32_USBB_UHCON (AVR32_USB_BASE+AVR32_USBB_UHCON_OFFSET)
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#define AVR32_USBB_UHINT (AVR32_USB_BASE+AVR32_USBB_UHINT_OFFSET)
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#define AVR32_USBB_UHINTCLR (AVR32_USB_BASE+AVR32_USBB_UHINTCLR_OFFSET)
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@ -542,6 +552,8 @@
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#define AVR32_UHDMA6_CONTROL (AVR32_USB_BASE+AVR32_UHDMA6_CONTROL_OFFSET)
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#define AVR32_UHDMA6_STATUS (AVR32_USB_BASE+AVR32_UHDMA6_STATUS_OFFSET)
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/* USB General Registers */
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#define AVR32_USBB_USBCON (AVR32_USB_BASE+AVR32_USBB_USBCON_OFFSET)
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#define AVR32_USBB_USBSTA (AVR32_USB_BASE+AVR32_USBB_USBSTA_OFFSET)
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#define AVR32_USBB_USBSTACLR (AVR32_USB_BASE+AVR32_USBB_USBSTACLR_OFFSET)
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@ -554,107 +566,177 @@
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#define AVR32_USBB_USBFSM (AVR32_USB_BASE+AVR32_USBB_USBFSM_OFFSET)
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/* Register Bit-field Definitions ***************************************************/
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/* USB Device Registers Bit-field Definitions ***************************************/
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/* Device General Control Register Bit-field Definitions */
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/* Device General Control Register */
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#define USBB_UDCON_
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/* Device Global Interrupt Register */
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#define USBB_UDINT_
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/* Device Global Interrupt Clear Register */
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#define USBB_UDINTCLR_
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/* Device Global Interrupt Set Register */
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#define USBB_UDINTSET_
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/* Device Global Interrupt Enable Register */
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#define USBB_UDINTE_
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/* Device Global Interrupt Enable Clear Register */
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#define USBB_UDINTECLR_
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/* Device Global Interrupt Enable Set Register */
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#define USBB_UDINTESET_
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/* Endpoint Enable/Reset Register */
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#define USBB_UERST_
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/* Device Frame Number Register */
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#define USBB_UDFNUM_
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#define USBB_UDCON_UADD_SHIFT (0) /* Bits 0-6: USB Address */
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#define USBB_UDCON_UADD_MASK (0x7f << USBB_UDCON_UADD_SHIFT)
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#define USBB_UDCON_ADDEN: (1 << 7) /* Bit 7: Address Enable */
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#define USBB_UDCON_DETACH (1 << 8) /* Bit 8: Detach */
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#define USBB_UDCON_RMWKUP (1 << 9) /* Bit 9: Remote Wake-Up */
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#define USBB_UDCON_LS (1 << 12) /* Bit 12: Low-Speed Mode Force */
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/* Endpoint Configuration Register */
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/* Device Global Interrupt Register Bit-field Definitions */
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/* Device Global Interrupt Clear Register Bit-field Definitions */
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/* Device Global Interrupt Set Register Bit-field Definitions */
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/* Device Global Interrupt Enable Register Bit-field Definitions */
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/* Device Global Interrupt Enable Clear Register Bit-field Definitions */
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/* Device Global Interrupt Enable Set Register Bit-field Definitions */
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#define USBB_UDINT_SUSP (1 << 0) /* Bit 0: Suspend Interrupt */
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#define USBB_UDINT_SOF (1 << 2) /* Bit 2: Start of Frame Interrupt */
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#define USBB_UDINT_EORST (1 << 3) /* Bit 3: End of Reset Interrupt */
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#define USBB_UDINT_WAKEUP (1 << 4) /* Bit 4: Wake-Up Interrupt */
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#define USBB_UDINT_EORSM (1 << 5) /* Bit 5: End of Resume Interrupt */
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#define USBB_UDINT_UPRSM (1 << 6) /* Bit 6: Upstream Resume Interrupt */
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#define USBB_UDINT_EPINT(n) (1 << ((n)+12)) /* Endpoint n Interrupt */
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#define USBB_UDINT_EP0INT (1 << 12) /* Bit 12: Endpoint n Interrupt */
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#define USBB_UDINT_EP1INT (1 << 13) /* Bit 13: Endpoint n Interrupt */
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#define USBB_UDINT_EP2INT (1 << 14) /* Bit 14: Endpoint n Interrupt */
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#define USBB_UDINT_EP3INT (1 << 15) /* Bit 15: Endpoint n Interrupt */
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#define USBB_UDINT_EP4INT (1 << 16) /* Bit 16: Endpoint n Interrupt */
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#define USBB_UDINT_EP5INT (1 << 17) /* Bit 17: Endpoint n Interrupt */
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#define USBB_UDINT_EP6INT (1 << 18) /* Bit 18: Endpoint n Interrupt */
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#define USBB_UDINT_DMAINT(n) (1 << ((n)+24)) /* DMA Channel n Interrupt */
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#define USBB_UDINT_DMA1INT (1 << 25) /* Bit 25: DMA Channel n Interrupt */
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#define USBB_UDINT_DMA2INT (1 << 26) /* Bit 26: DMA Channel 1 Interrupt */
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#define USBB_UDINT_DMA3INT (1 << 27) /* Bit 27: DMA Channel 2 Interrupt */
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#define USBB_UDINT_DMA4INT (1 << 28) /* Bit 28: DMA Channel 3 Interrupt */
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#define USBB_UDINT_DMA5INT (1 << 29) /* Bit 29: DMA Channel 4 Interrupt */
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#define USBB_UDINT_DMA6INT (1 << 30) /* Bit 30: DMA Channel 5 Interrupt */
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/* Endpoint Enable/Reset Register Bit-field Definitions */
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#define USBB_UERST_EPRST(n) (1 << ((n)+16)) /* Endpoint n Reset */
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#define USBB_UERST_EPRST0 (1 << 16) /* Bit 16: Endpoint 0 Reset */
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#define USBB_UERST_EPRST1 (1 << 17) /* Bit 17: Endpoint 1 Reset */
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#define USBB_UERST_EPRST2 (1 << 18) /* Bit 18: Endpoint 2 Reset */
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#define USBB_UERST_EPRST3 (1 << 19) /* Bit 19: Endpoint 3 Reset */
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#define USBB_UERST_EPRST4 (1 << 20) /* Bit 20: Endpoint 4 Reset */
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#define USBB_UERST_EPRST5 (1 << 21) /* Bit 21: Endpoint 5 Reset */
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#define USBB_UERST_EPRST6 (1 << 22) /* Bit 22: Endpoint 6 Reset */
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#define USBB_UERST_EPEN(n) (1 << n) /* Endpoint n Enable */
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#define USBB_UERST_EPEN0 (1 << 0) /* Bit 0: Endpoint 0 Enable */
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#define USBB_UERST_EPEN1 (1 << 1) /* Bit 1: Endpoint 1 Enable */
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#define USBB_UERST_EPEN2 (1 << 2) /* Bit 2: Endpoint 2 Enable */
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#define USBB_UERST_EPEN3 (1 << 3) /* Bit 3: Endpoint 3 Enable */
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#define USBB_UERST_EPEN4 (1 << 4) /* Bit 4: Endpoint 4 Enable */
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#define USBB_UERST_EPEN5 (1 << 5) /* Bit 5: Endpoint 5 Enable */
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#define USBB_UERST_EPEN6 (1 << 6) /* Bit 5: Endpoint 6 Enable */
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/* Device Frame Number Register Bit-field Definitions */
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#define USBB_UDFNUM_FNUM_SHIFT (3) /* Bits 3-13: Frame Number */
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#define USBB_UDFNUM_FNUM_MASK (0x7ff << USBB_UDFNUM_FNUM_SHIFT)
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#define USBB_UDFNUM_FNCERR (1 << 15) /* Bit 15: Frame Number CRC Error */
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/* Endpoint Configuration Register Bit-field Definitions */
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#define USBB_UECFG_
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/* Endpoint Status Register */
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/* Endpoint Status Register Bit-field Definitions */
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#define USBB_UESTA_
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/* Endpoint Status Clear Register */
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/* Endpoint Status Clear Register Bit-field Definitions */
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#define USBB_UESTACLR_
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/* Endpoint Status Set Register */
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/* Endpoint Status Set Register Bit-field Definitions */
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#define USBB_UESTASET_
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/* Endpoint Control Register */
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/* Endpoint Control Register Bit-field Definitions */
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#define USBB_UECON_
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/* Endpoint Control Set Register */
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/* Endpoint Control Set Register Bit-field Definitions */
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#define USBB_UECONSET_
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/* Endpoint Control Clear Register */
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/* Endpoint Control Clear Register Bit-field Definitions */
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#define USBB_UECONCLR_
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/* Device DMA Channel Next Descriptor Address Register */
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/* Device DMA Channel Next Descriptor Address Register Bit-field Definitions */
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#define UDDMA_NEXTDESC_
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/* Device DMA Channel HSB Address Register */
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#define UDDMA_ADDR_
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/* Device DMA Channel Control Register */
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/* Device DMA Channel HSB Address Register Bit-field Definitions */
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/* This register holds a 32-bit address with internal bit fields */
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/* Device DMA Channel Control Register Bit-field Definitions */
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#define UDDMA_CONTROL_
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/* Device DMA Channel Status Register */
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/* Device DMA Channel Status Register Bit-field Definitions */
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#define UDDMA_STATUS_
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/* Host General Control Register */
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/* USB Host Registers Bit-field Definitions *********************************/
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/* Host General Control Register Bit-field Definitions */
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#define USBB_UHCON_
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/* Host Global Interrupt Register */
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/* Host Global Interrupt Register Bit-field Definitions */
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#define USBB_UHINT_
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/* Host Global Interrupt Clear Register */
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/* Host Global Interrupt Clear Register Bit-field Definitions */
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#define USBB_UHINTCLR_
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/* Host Global Interrupt Set Register */
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/* Host Global Interrupt Set Register Bit-field Definitions */
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#define USBB_UHINTSET_
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/* Host Global Interrupt Enable Register */
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/* Host Global Interrupt Enable Register Bit-field Definitions */
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#define USBB_UHINTE_
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/* Host Global Interrupt Enable Clear Register */
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/* Host Global Interrupt Enable Clear Register Bit-field Definitions */
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#define USBB_UHINTECLR_
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/* Host Global Interrupt Enable Set Register */
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/* Host Global Interrupt Enable Set Register Bit-field Definitions */
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#define USBB_UHINTESET_
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/* Pipe Enable/Reset Register */
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/* Pipe Enable/Reset Register Bit-field Definitions */
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#define USBB_UPRST_
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/* Host Frame Number Register */
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/* Host Frame Number Register Bit-field Definitions */
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#define USBB_UHFNUM_
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/* Host Address 1 Register */
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/* Host Address 1 Register Bit-field Definitions */
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#define USBB_UHADDR1_
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/* Host Address 2 Register */
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/* Host Address 2 Register Bit-field Definitions */
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#define USBB_UHADDR2_
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/* Pipe Configuration Register */
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/* Pipe Configuration Register Bit-field Definitions */
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#define USBB_UPCFG_
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/* Pipe Status Register */
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/* Pipe Status Register Bit-field Definitions */
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#define USBB_UPSTA_
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/* Pipe Status Clear Register */
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/* Pipe Status Clear Register Bit-field Definitions */
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#define USBB_UPSTACLR_
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/* Pipe Status Set Register */
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/* Pipe Status Set Register Bit-field Definitions */
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#define USBB_UPSTASET_
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/* Pipe Control Register */
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/* Pipe Control Register Bit-field Definitions */
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#define USBB_UPCON_
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/* Pipe Control Set Register */
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/* Pipe Control Set Register Bit-field Definitions */
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#define USBB_UPCONSET_
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/* Pipe Control Clear Register */
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/* Pipe Control Clear Register Bit-field Definitions */
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#define USBB_UPCONCLR_
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/* Pipe IN Request Register */
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/* Pipe IN Request Register Bit-field Definitions */
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#define USBB_UPINRQ_
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/* Pipe Error Register */
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/* Pipe Error Register Bit-field Definitions */
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#define USBB_UPERR_
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/* Host DMA Channel Next Descriptor Address Register */
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/* Host DMA Channel Next Descriptor Address Register Bit-field Definitions */
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#define UHDMA_NEXTDESC_
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/* Host DMA Channel HSB Address Register */
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#define UHDMA_ADDR_
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/* Host DMA Channel Control Register */
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/* Host DMA Channel HSB Address Register Bit-field Definitions */
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/* This register holds a 32-bit address with internal bit fields */
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/* Host DMA Channel Control Register Bit-field Definitions */
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#define UHDMA_CONTROL_
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/* Host DMA Channel Status Register */
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/* Host DMA Channel Status Register Bit-field Definitions */
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#define UHDMA_STATUS_
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/* General Control Register */
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#define USBB_USBCON_
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/* USB General Registers Bit-field Definitions ******************************/
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/* General Status Register */
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/* General Status Clear Register */
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/* General Status Set Register */
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/* General Control Register Bit-field Definitions */
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#define USBB_USBCON_IDTE (1 << 0) /* Bit 0: ID Transition Interrupt Enable */
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#define USBB_USBCON_VBUSTE (1 << 1) /* Bit 1: VBus Transition Interrupt Enable */
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#define USBB_USBCON_VBERRE (1 << 3) /* Bit 3: VBus Error Interrupt Enable */
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#define USBB_USBCON_BCERRE (1 << 4) /* Bit 4: B-Connection Error Interrupt Enable */
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#define USBB_USBCON_ROLEEXE (1 << 5) /* Bit 5: Role Exchange Interrupt Enable */
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#define USBB_USBCON_STOE (1 << 7) /* Bit 7: Suspend Time-Out Interrupt Enable */
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#define USBB_USBCON_VBUSHWC (1 << 8) /* Bit 8: VBus Hardware Control */
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#define USBB_USBCON_OTGPADE (1 << 12) /* Bit 12: OTG Pad Enable */
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#define USBB_USBCON_VBUSPO (1 << 13) /* Bit 13: VBus Polarity */
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#define USBB_USBCON_FRZCLK (1 << 14) /* Bit 14: Freeze USB Clock */
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#define USBB_USBCON_USBE (1 << 15) /* Bit 15: USBB Enable */
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#define USBB_USBCON_TIMVALUE_SHIFT (16) /* Bits 16-17: Timmer Value */
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#define USBB_USBCON_TIMVALUE_MASK (3 << USBB_USBCON_TIMVALUE_SHIFT)
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#define USBB_USBCON_TIMPAGE_SHIFT (20) /* Bits 20-21: Timer Page */
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#define USBB_USBCON_TIMPAGE_MASK (3 << USBB_USBCON_TIMPAGE_SHIFT)
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#define USBB_USBCON_UNLOCK (1 << 22) /* Bit 22: Timer Access Unlock */
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#define USBB_USBCON_UIDE (1 << 24) /* Bit 24: USB_ID Pin Enable */
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#define USBB_USBCON_UIMOD (1 << 25) /* Bit 25: USBB Mode */
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/* General Status Register Bit-field Definitions */
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/* General Status Clear Register Bit-field Definitions */
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/* General Status Set Register Bit-field Definitions */
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#define USBB_USBSTA_IDTI (1 << 0) /* Bit 0: ID Transition Interrupt */
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#define USBB_USBSTA_VBUSTI (1 << 1) /* Bit 1: VBus Transition Interrupt */
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#define USBB_USBSTA_SPEED_SHIFT (12) /* Bits 12-13: Speed Status (read-only) */
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#define USBB_USBSTA_SPEED_MASK (3 << USBB_USBSTA_SPEED_SHIFT)
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# define USBB_USBSTA_SPEED_FULL (0 << USBB_USBSTA_SPEED_SHIFT) /* Full-Speed mode */
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# define USBB_USBSTA_SPEED_FULL (2 << USBB_USBSTA_SPEED_SHIFT) /* Low-Speed mode */
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# define USBB_USBSTA_SPEED_LOW (2 << USBB_USBSTA_SPEED_SHIFT) /* Low-Speed mode */
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/* IP Version Register */
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/* IP Version Register Bit-field Definitions */
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#define USBB_UVERS_SHIFT (0) /* Bits 0-11: Version Number */
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#define USBB_UVERS_MASK (0xfff << USBB_UVERS_SHIFT)
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#define USBB_UVERS_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
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#define USBB_UVERS_VARIANT_MASK (15 << USBB_UVERS_VARIANT_SHIFT)
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/* IP Features Register */
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/* IP Features Register Bit-field Definitions */
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#define USBB_UFEAT_EPTNBRMAX_SHIFT (0) /* Bits 0-3: Maximal Number of Pipes/Endpoints */
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#define USBB_UFEAT_EPTNBRMAX_MASK (15 << USBB_UFEAT_EPTNBRMAX_SHIFT)
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@ -700,14 +782,31 @@
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# define USBB_UFEAT_FIFOMAXSZ_GE16K (7 << USBB_UFEAT_FIFOMAXSZ_SHIFT) /* >= 16384 bytes */
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#define USBB_UFEAT_BWRDPRAM (1 << 15) /* Bit 15: DPRAM Byte-Write Capability */
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/* IP PB Address Size Register */
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#define USBB_UADDRSIZE_
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/* IP Name Register 1 */
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#define USBB_UNAME1_
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/* IP Name Register 2 */
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#define USBB_UNAME2_
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/* USB Finite State Machine Status Register */
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#define USBB_USBFSM_
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/* IP PB Address Size Register Bit-field Definitions */
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/* IP Name Register 1 Bit-field Definitions */
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/* IP Name Register 2 Bit-field Definitions */
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/* These registers contain a 32-value and, hence, have no bit fields */
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/* USB Finite State Machine Status Register Bit-field Definitions */
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#define USBB_USBFSM_MASK (15)
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# define USBB_USBFSM_A_IDLESTATE (0)
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# define USBB_USBFSM_A_WAITVRISE (1)
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# define USBB_USBFSM_A_WAITBCON (2)
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# define USBB_USBFSM_A_HOST (3)
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# define USBB_USBFSM_A_SUSPEND (4)
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# define USBB_USBFSM_A_PERIPHERAL (5)
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# define USBB_USBFSM_A_WAITVFALL (6)
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# define USBB_USBFSM_A_VBUSERR (7)
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# define USBB_USBFSM_A_WAITDISCHARGE (8)
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# define USBB_USBFSM_B_IDLE (9)
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# define USBB_USBFSM_B_PERIPHERAL (10)
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# define USBB_USBFSM_B_WAITBEGINHNP (11)
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# define USBB_USBFSM_B_WAITDISCHARGE (12)
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# define USBB_USBFSM_B_WAITACON (13)
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# define USBB_USBFSM_B_HOST (14)
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# define USBB_USBFSM_B_SRPINIT (15)
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(1 << xxx) /* Bit xxx:
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_SHIFT (xxx) /* Bits xxx-xxx:
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