From 38858b6cc35d51e6fdf13b6eeeed7f45aeee523d Mon Sep 17 00:00:00 2001 From: xuxingliang Date: Thu, 18 Jul 2024 20:36:22 +0800 Subject: [PATCH] arch: set current regs firstly in undefinedinsn Need to save the regs firstly in case syslog triggers another crash. Otherwise we may loose the register contents for the first exception. Signed-off-by: xuxingliang --- arch/arm/src/arm/arm_undefinedinsn.c | 8 ++++++-- arch/arm/src/armv7-a/arm_undefinedinsn.c | 8 ++++++-- arch/arm/src/armv7-r/arm_undefinedinsn.c | 8 ++++++-- arch/arm/src/armv8-r/arm_undefinedinsn.c | 8 ++++++-- 4 files changed, 24 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/arm/arm_undefinedinsn.c b/arch/arm/src/arm/arm_undefinedinsn.c index fb20aced9e..0aeeb19076 100644 --- a/arch/arm/src/arm/arm_undefinedinsn.c +++ b/arch/arm/src/arm/arm_undefinedinsn.c @@ -42,6 +42,12 @@ void arm_undefinedinsn(uint32_t *regs) { + /* Save the saved processor context in current_regs where it can be + * accessed for register dumps and possibly context switching. + */ + + up_set_current_regs(regs); + if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext) { _alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n", @@ -52,7 +58,5 @@ void arm_undefinedinsn(uint32_t *regs) _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); } - up_set_current_regs(regs); - PANIC_WITH_REGS("panic", regs); } diff --git a/arch/arm/src/armv7-a/arm_undefinedinsn.c b/arch/arm/src/armv7-a/arm_undefinedinsn.c index 7a6fc8ef57..8acd6eb96d 100644 --- a/arch/arm/src/armv7-a/arm_undefinedinsn.c +++ b/arch/arm/src/armv7-a/arm_undefinedinsn.c @@ -42,6 +42,12 @@ uint32_t *arm_undefinedinsn(uint32_t *regs) { + /* Save the saved processor context in current_regs where it can be + * accessed for register dumps and possibly context switching. + */ + + up_set_current_regs(regs); + if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext) { _alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n", @@ -52,8 +58,6 @@ uint32_t *arm_undefinedinsn(uint32_t *regs) _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); } - up_set_current_regs(regs); - PANIC_WITH_REGS("panic", regs); return regs; /* To keep the compiler happy */ } diff --git a/arch/arm/src/armv7-r/arm_undefinedinsn.c b/arch/arm/src/armv7-r/arm_undefinedinsn.c index 6e069cbc40..a62d872f02 100644 --- a/arch/arm/src/armv7-r/arm_undefinedinsn.c +++ b/arch/arm/src/armv7-r/arm_undefinedinsn.c @@ -42,6 +42,12 @@ uint32_t *arm_undefinedinsn(uint32_t *regs) { + /* Save the saved processor context in current_regs where it can be + * accessed for register dumps and possibly context switching. + */ + + up_set_current_regs(regs); + if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext) { _alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n", @@ -52,8 +58,6 @@ uint32_t *arm_undefinedinsn(uint32_t *regs) _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); } - up_set_current_regs(regs); - PANIC_WITH_REGS("panic", regs); return regs; /* To keep the compiler happy */ } diff --git a/arch/arm/src/armv8-r/arm_undefinedinsn.c b/arch/arm/src/armv8-r/arm_undefinedinsn.c index 47568d953e..35e13306ed 100644 --- a/arch/arm/src/armv8-r/arm_undefinedinsn.c +++ b/arch/arm/src/armv8-r/arm_undefinedinsn.c @@ -42,6 +42,12 @@ uint32_t *arm_undefinedinsn(uint32_t *regs) { + /* Save the saved processor context in current_regs where it can be + * accessed for register dumps and possibly context switching. + */ + + up_set_current_regs(regs); + if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext) { _alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n", @@ -52,8 +58,6 @@ uint32_t *arm_undefinedinsn(uint32_t *regs) _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); } - up_set_current_regs(regs); - PANIC_WITH_REGS("panic", regs); return regs; /* To keep the compiler happy */ }