arch/stm32: Fix a wrong bitfield definition
arch/arm/src/stm32/hardware/stm32_adc_v2.h: * ADC_CFGR1_JAWD1EN: Change from (1 << 22) to (1 << 24) and update comment.
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@ -465,7 +465,7 @@
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#define ADC_CFGR1_JQM (1 << 21) /* Bit 21: JSQR queue mode */
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#define ADC_CFGR1_JQM (1 << 21) /* Bit 21: JSQR queue mode */
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#define ADC_CFGR1_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */
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#define ADC_CFGR1_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */
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#define ADC_CFGR1_AWD1EN (1 << 23) /* Bit 23: Analog watchdog enable 1 regular channels */
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#define ADC_CFGR1_AWD1EN (1 << 23) /* Bit 23: Analog watchdog enable 1 regular channels */
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#define ADC_CFGR1_JAWD1EN (1 << 22) /* Bit 22: Analog watchdog enable 1 injected channels */
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#define ADC_CFGR1_JAWD1EN (1 << 24) /* Bit 24: Analog watchdog enable 1 injected channels */
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#define ADC_CFGR1_JAUTO (1 << 25) /* Bit 25: Automatic Injected Group conversion */
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#define ADC_CFGR1_JAUTO (1 << 25) /* Bit 25: Automatic Injected Group conversion */
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#define ADC_CFGR1_AWD1CH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */
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#define ADC_CFGR1_AWD1CH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */
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#define ADC_CFGR1_AWD1CH_MASK (31 << ADC_CFGR1_AWD1CH_SHIFT)
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#define ADC_CFGR1_AWD1CH_MASK (31 << ADC_CFGR1_AWD1CH_SHIFT)
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