From 32894cda1c8f8584417498d80ac2037a1dd8792c Mon Sep 17 00:00:00 2001 From: Alin Jerpelea Date: Sun, 28 Mar 2021 15:06:35 +0200 Subject: [PATCH] arch: arm: sam: fix Mixed Case Errors fix Mixed Case Errors to pass CI Signed-off-by: Alin Jerpelea --- arch/arm/src/sama5/hardware/sam_can.h | 54 +++++++++---------- arch/arm/src/sama5/sam_can.c | 44 +++++++-------- arch/arm/src/sama5/sam_pmecc.c | 6 +-- arch/arm/src/samd2l2/sam_sercom.c | 10 ++-- arch/arm/src/samd5e5/hardware/sam_gclk.h | 2 +- arch/arm/src/samd5e5/sam_sercom.c | 6 +-- boards/arm/samd5e5/metro-m4/include/board.h | 2 +- .../same54-xplained-pro/include/board.h | 2 +- 8 files changed, 63 insertions(+), 63 deletions(-) diff --git a/arch/arm/src/sama5/hardware/sam_can.h b/arch/arm/src/sama5/hardware/sam_can.h index 2911707dc4..cb2636a09a 100644 --- a/arch/arm/src/sama5/hardware/sam_can.h +++ b/arch/arm/src/sama5/hardware/sam_can.h @@ -52,7 +52,7 @@ #define SAM_CAN_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ #define SAM_CAN_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ -#define SAM_CAN_MBn_OFFSET(n) (0x0200 + ((n) << 5)) +#define SAM_CAN_MBN_OFFSET(n) (0x0200 + ((n) << 5)) #define SAM_CAN_MMR_OFFSET 0x0000 /* Mailbox Mode Register */ #define SAM_CAN_MAM_OFFSET 0x0004 /* Mailbox Acceptance Mask Register */ #define SAM_CAN_MID_OFFSET 0x0008 /* Mailbox ID Register */ @@ -62,14 +62,14 @@ #define SAM_CAN_MDH_OFFSET 0x0018 /* Mailbox Data High Register */ #define SAM_CAN_MCR_OFFSET 0x001c /* Mailbox Control Register */ -#define SAM_CAN_MnMR_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MMR_OFFSET) -#define SAM_CAN_MnAM_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MAM_OFFSET) -#define SAM_CAN_MnID_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MID_OFFSET) -#define SAM_CAN_MnFID_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MFID_OFFSET) -#define SAM_CAN_MnSR_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MSR_OFFSET) -#define SAM_CAN_MnDL_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MDL_OFFSET) -#define SAM_CAN_MnDH_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MDH_OFFSET) -#define SAM_CAN_MnCR_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MCR_OFFSET) +#define SAM_CAN_MNMR_OFFSET(n) (SAM_CAN_MBN_OFFSET(n)+SAM_CAN_MMR_OFFSET) +#define SAM_CAN_MNAM_OFFSET(n) (SAM_CAN_MBN_OFFSET(n)+SAM_CAN_MAM_OFFSET) +#define SAM_CAN_MNID_OFFSET(n) (SAM_CAN_MBN_OFFSET(n)+SAM_CAN_MID_OFFSET) +#define SAM_CAN_MNFID_OFFSET(n) (SAM_CAN_MBN_OFFSET(n)+SAM_CAN_MFID_OFFSET) +#define SAM_CAN_MNSR_OFFSET(n) (SAM_CAN_MBN_OFFSET(n)+SAM_CAN_MSR_OFFSET) +#define SAM_CAN_MNDL_OFFSET(n) (SAM_CAN_MBN_OFFSET(n)+SAM_CAN_MDL_OFFSET) +#define SAM_CAN_MNDH_OFFSET(n) (SAM_CAN_MBN_OFFSET(n)+SAM_CAN_MDH_OFFSET) +#define SAM_CAN_MNCR_OFFSET(n) (SAM_CAN_MBN_OFFSET(n)+SAM_CAN_MCR_OFFSET) /* CAN Register Addresses ***************************************************/ @@ -88,15 +88,15 @@ #define SAM_CAN0_WPMR (SAM_CAN0_VBASE+SAM_CAN_WPMR_OFFSET) #define SAM_CAN0_WPSR (SAM_CAN0_VBASE+SAM_CAN_WPSR_OFFSET) -#define SAM_CAN0_MB_BASE(n) (SAM_CAN0_VBASE+SAM_CAN_MBn_OFFSET(n)) -#define SAM_CAN0_MMR(n) (SAM_CAN0_VBASE+SAM_CAN_MnMR_OFFSET(n)) -#define SAM_CAN0_MAM(n) (SAM_CAN0_VBASE+SAM_CAN_MnAM_OFFSET(n)) -#define SAM_CAN0_MID(n) (SAM_CAN0_VBASE+SAM_CAN_MnID_OFFSET(n)) -#define SAM_CAN0_MFID(n) (SAM_CAN0_VBASE+SAM_CAN_MnFID_OFFSET(n)) -#define SAM_CAN0_MSR(n) (SAM_CAN0_VBASE+SAM_CAN_MnSR_OFFSET(n)) -#define SAM_CAN0_MDL(n) (SAM_CAN0_VBASE+SAM_CAN_MnDL_OFFSET(n)) -#define SAM_CAN0_MDH(n) (SAM_CAN0_VBASE+SAM_CAN_MnDH_OFFSET(n)) -#define SAM_CAN0_MCR(n) (SAM_CAN0_VBASE+SAM_CAN_MnCR_OFFSET(n)) +#define SAM_CAN0_MB_BASE(n) (SAM_CAN0_VBASE+SAM_CAN_MBN_OFFSET(n)) +#define SAM_CAN0_MMR(n) (SAM_CAN0_VBASE+SAM_CAN_MNMR_OFFSET(n)) +#define SAM_CAN0_MAM(n) (SAM_CAN0_VBASE+SAM_CAN_MNAM_OFFSET(n)) +#define SAM_CAN0_MID(n) (SAM_CAN0_VBASE+SAM_CAN_MNID_OFFSET(n)) +#define SAM_CAN0_MFID(n) (SAM_CAN0_VBASE+SAM_CAN_MNFID_OFFSET(n)) +#define SAM_CAN0_MSR(n) (SAM_CAN0_VBASE+SAM_CAN_MNSR_OFFSET(n)) +#define SAM_CAN0_MDL(n) (SAM_CAN0_VBASE+SAM_CAN_MNDL_OFFSET(n)) +#define SAM_CAN0_MDH(n) (SAM_CAN0_VBASE+SAM_CAN_MNDH_OFFSET(n)) +#define SAM_CAN0_MCR(n) (SAM_CAN0_VBASE+SAM_CAN_MNCR_OFFSET(n)) #define SAM_CAN1_MR (SAM_CAN1_VBASE+SAM_CAN_MR_OFFSET) #define SAM_CAN1_IER (SAM_CAN1_VBASE+SAM_CAN_IER_OFFSET) @@ -113,15 +113,15 @@ #define SAM_CAN1_WPMR (SAM_CAN1_VBASE+SAM_CAN_WPMR_OFFSET) #define SAM_CAN1_WPSR (SAM_CAN1_VBASE+SAM_CAN_WPSR_OFFSET) -#define SAM_CAN1_MB_BASE(n) (SAM_CAN1_VBASE+SAM_CAN_MBn_OFFSET(n)) -#define SAM_CAN1_MMR(n) (SAM_CAN1_VBASE+SAM_CAN_MnMR_OFFSET(n)) -#define SAM_CAN1_MAM(n) (SAM_CAN1_VBASE+SAM_CAN_MnAM_OFFSET(n)) -#define SAM_CAN1_MID(n) (SAM_CAN1_VBASE+SAM_CAN_MnID_OFFSET(n)) -#define SAM_CAN1_MFID(n) (SAM_CAN1_VBASE+SAM_CAN_MnFID_OFFSET(n)) -#define SAM_CAN1_MSR(n) (SAM_CAN1_VBASE+SAM_CAN_MnSR_OFFSET(n)) -#define SAM_CAN1_MDL(n) (SAM_CAN1_VBASE+SAM_CAN_MnDL_OFFSET(n)) -#define SAM_CAN1_MDH(n) (SAM_CAN1_VBASE+SAM_CAN_MnDH_OFFSET(n)) -#define SAM_CAN1_MCR(n) (SAM_CAN1_VBASE+SAM_CAN_MnCR_OFFSET(n)) +#define SAM_CAN1_MB_BASE(n) (SAM_CAN1_VBASE+SAM_CAN_MBN_OFFSET(n)) +#define SAM_CAN1_MMR(n) (SAM_CAN1_VBASE+SAM_CAN_MNMR_OFFSET(n)) +#define SAM_CAN1_MAM(n) (SAM_CAN1_VBASE+SAM_CAN_MNAM_OFFSET(n)) +#define SAM_CAN1_MID(n) (SAM_CAN1_VBASE+SAM_CAN_MNID_OFFSET(n)) +#define SAM_CAN1_MFID(n) (SAM_CAN1_VBASE+SAM_CAN_MNFID_OFFSET(n)) +#define SAM_CAN1_MSR(n) (SAM_CAN1_VBASE+SAM_CAN_MNSR_OFFSET(n)) +#define SAM_CAN1_MDL(n) (SAM_CAN1_VBASE+SAM_CAN_MNDL_OFFSET(n)) +#define SAM_CAN1_MDH(n) (SAM_CAN1_VBASE+SAM_CAN_MNDH_OFFSET(n)) +#define SAM_CAN1_MCR(n) (SAM_CAN1_VBASE+SAM_CAN_MNCR_OFFSET(n)) /* CAN Register Bit Definitions *********************************************/ diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c index 5f6789588b..cde01575e6 100644 --- a/arch/arm/src/sama5/sam_can.c +++ b/arch/arm/src/sama5/sam_can.c @@ -535,7 +535,7 @@ static void can_dumpmbregs(FAR struct sam_can_s *priv, FAR const char *msg) for (i = 0; i < SAM_CAN_NMAILBOXES; i++) { - mbbase = config->base + SAM_CAN_MBn_OFFSET(i); + mbbase = config->base + SAM_CAN_MBN_OFFSET(i); caninfo(" MB%d:\n", i); /* CAN mailbox registers */ @@ -685,7 +685,7 @@ static void can_mbfree(FAR struct sam_can_s *priv, int mbndx) /* Disable the mailbox */ - can_putreg(priv, SAM_CAN_MnMR_OFFSET(mbndx), 0); + can_putreg(priv, SAM_CAN_MNMR_OFFSET(mbndx), 0); /* Free the mailbox by clearing the corresponding bit in the freemb and * txmbset (only TX mailboxes are freed in this way. @@ -750,14 +750,14 @@ static int can_recvsetup(FAR struct sam_can_s *priv) */ #ifdef CONFIG_CAN_EXTID - can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx), + can_putreg(priv, SAM_CAN_MNID_OFFSET(mbndx), CAN_MID_EXTID(config->filter[mbno].addr)); - can_putreg(priv, SAM_CAN_MnAM_OFFSET(mbndx), + can_putreg(priv, SAM_CAN_MNAM_OFFSET(mbndx), CAN_MAM_EXTID(config->filter[mbno].mask)); #else - can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx), + can_putreg(priv, SAM_CAN_MNID_OFFSET(mbndx), CAN_MID_STDID(config->filter[mbno].addr)); - can_putreg(priv, SAM_CAN_MnAM_OFFSET(mbndx), + can_putreg(priv, SAM_CAN_MNAM_OFFSET(mbndx), CAN_MAM_STDID(config->filter[mbno].mask)); #endif @@ -768,11 +768,11 @@ static int can_recvsetup(FAR struct sam_can_s *priv) * multipart messages. */ - can_putreg(priv, SAM_CAN_MnMR_OFFSET(mbndx), CAN_MMR_MOT_RX); + can_putreg(priv, SAM_CAN_MNMR_OFFSET(mbndx), CAN_MMR_MOT_RX); /* Clear pending interrupts and start reception of the next message */ - can_putreg(priv, SAM_CAN_MnCR_OFFSET(mbndx), CAN_MCR_MTCR); + can_putreg(priv, SAM_CAN_MNCR_OFFSET(mbndx), CAN_MCR_MTCR); /* Enable interrupts from this mailbox */ @@ -825,7 +825,7 @@ static void can_reset(FAR struct can_dev_s *dev) for (i = 0; i < SAM_CAN_NMAILBOXES; i++) { - can_putreg(priv, SAM_CAN_MnMR_OFFSET(i), 0); + can_putreg(priv, SAM_CAN_MNMR_OFFSET(i), 0); } /* All mailboxes are again available */ @@ -1159,17 +1159,17 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) #ifdef CONFIG_CAN_EXTID DEBUGASSERT(msg->cm_hdr.ch_extid); DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 29)); - can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx), + can_putreg(priv, SAM_CAN_MNID_OFFSET(mbndx), CAN_MID_EXTID(msg->cm_hdr.ch_id)); #else DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 11)); - can_putreg(priv, SAM_CAN_MnID_OFFSET(mbndx), + can_putreg(priv, SAM_CAN_MNID_OFFSET(mbndx), CAN_MID_STDID(msg->cm_hdr.ch_id)); #endif /* Enable transmit mode */ - can_putreg(priv, SAM_CAN_MnMR_OFFSET(mbndx), CAN_MMR_MOT_TX); + can_putreg(priv, SAM_CAN_MNMR_OFFSET(mbndx), CAN_MMR_MOT_TX); /* After Transmit Mode is enabled, the MRDY flag in the CAN_MSR register * is automatically set until the first command is sent. When the MRDY @@ -1179,7 +1179,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) * message data length in the CAN_MCRx register. */ - DEBUGASSERT((can_getreg(priv, SAM_CAN_MnSR_OFFSET(mbndx)) & + DEBUGASSERT((can_getreg(priv, SAM_CAN_MNSR_OFFSET(mbndx)) & CAN_MSR_MRDY) != 0); /* Bytes are received/sent on the bus in the following order: @@ -1205,18 +1205,18 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) ptr = msg->cm_data; regval = CAN_MDL0(ptr[0]) | CAN_MDL1(ptr[1]) | CAN_MDL2(ptr[2]) | CAN_MDL3(ptr[3]); - can_putreg(priv, SAM_CAN_MnDL_OFFSET(mbndx), regval); + can_putreg(priv, SAM_CAN_MNDL_OFFSET(mbndx), regval); regval = CAN_MDH4(ptr[4]) | CAN_MDH5(ptr[5]) | CAN_MDH6(ptr[6]) | CAN_MDH7(ptr[7]); - can_putreg(priv, SAM_CAN_MnDH_OFFSET(mbndx), regval); + can_putreg(priv, SAM_CAN_MNDH_OFFSET(mbndx), regval); /* Set the DLC value in the CAN_MCRx register. Set the MTCR register * clearing MRDY, and indicating that the message is ready to be sent. */ regval = CAN_MCR_MDLC(msg->cm_hdr.ch_dlc) | CAN_MCR_MTCR; - can_putreg(priv, SAM_CAN_MnCR_OFFSET(mbndx), regval); + can_putreg(priv, SAM_CAN_MNCR_OFFSET(mbndx), regval); /* If we have not been asked to suppress TX interrupts, then enable * interrupts from this mailbox now. @@ -1337,8 +1337,8 @@ static inline void can_rxinterrupt(FAR struct can_dev_s *dev, int mbndx, # warning REVISIT #endif - md[0] = can_getreg(priv, SAM_CAN_MnDH_OFFSET(mbndx)); - md[1] = can_getreg(priv, SAM_CAN_MnDL_OFFSET(mbndx)); + md[0] = can_getreg(priv, SAM_CAN_MNDH_OFFSET(mbndx)); + md[1] = can_getreg(priv, SAM_CAN_MNDL_OFFSET(mbndx)); /* Get the ID associated with the newly received message: )nce a new * message is received, its ID is masked with the CAN_MAMx value and @@ -1346,7 +1346,7 @@ static inline void can_rxinterrupt(FAR struct can_dev_s *dev, int mbndx, * copied to the CAN_MIDx register. */ - mid = can_getreg(priv, SAM_CAN_MnID_OFFSET(mbndx)); + mid = can_getreg(priv, SAM_CAN_MNID_OFFSET(mbndx)); /* Format the CAN header. * REVISIT: This logic should be capable of receiving standard messages @@ -1384,7 +1384,7 @@ static inline void can_rxinterrupt(FAR struct can_dev_s *dev, int mbndx, * requests a new RX transfer. */ - can_putreg(priv, SAM_CAN_MnCR_OFFSET(mbndx), CAN_MCR_MTCR); + can_putreg(priv, SAM_CAN_MNCR_OFFSET(mbndx), CAN_MCR_MTCR); } /**************************************************************************** @@ -1451,12 +1451,12 @@ static inline void can_mbinterrupt(FAR struct can_dev_s *dev, int mbndx) * register. */ - msr = can_getreg(priv, SAM_CAN_MnSR_OFFSET(mbndx)); + msr = can_getreg(priv, SAM_CAN_MNSR_OFFSET(mbndx)); if ((msr & (CAN_MSR_MRDY | CAN_MSR_MABT)) != 0) { /* Handle the result based on how the mailbox was configured */ - mmr = can_getreg(priv, SAM_CAN_MnMR_OFFSET(mbndx)); + mmr = can_getreg(priv, SAM_CAN_MNMR_OFFSET(mbndx)); switch (mmr & CAN_MMR_MOT_MASK) { case CAN_MMR_MOT_RX: /* Reception Mailbox */ diff --git a/arch/arm/src/sama5/sam_pmecc.c b/arch/arm/src/sama5/sam_pmecc.c index d756d6f30c..13bceed466 100644 --- a/arch/arm/src/sama5/sam_pmecc.c +++ b/arch/arm/src/sama5/sam_pmecc.c @@ -145,11 +145,11 @@ struct sam_pmecc_s /* This is the type of the ROM detection/correction function * - * REVISIT: Where are the types Pmecc and Pmerrloc? + * REVISIT: Where are the types pmecc and pmerrloc? */ #ifdef CONFIG_SAMA5_PMECC_EMBEDDEDALGO -typedef uint32_t (*pmecc_correctionalgo_t)(Pmecc *, Pmerrloc *, +typedef uint32_t (*pmecc_correctionalgo_t)(pmecc *, pmerrloc *, struct pmecc_desc_s *desc, uint32_t isr, uintptr_t data); #endif @@ -1328,7 +1328,7 @@ void pmecc_unlock(void) int pmecc_correction(uint32_t isr, uintptr_t data) { #ifdef CONFIG_SAMA5_PMECC_EMBEDDEDALGO - /* REVISIT: Whare are the types Pmecc and Pmerrloc? + /* REVISIT: Whare are the types pmecc and pmerrloc? * REVISIT: Check returned value */ diff --git a/arch/arm/src/samd2l2/sam_sercom.c b/arch/arm/src/samd2l2/sam_sercom.c index 93f97ba20a..c49c265178 100644 --- a/arch/arm/src/samd2l2/sam_sercom.c +++ b/arch/arm/src/samd2l2/sam_sercom.c @@ -81,12 +81,12 @@ void sercom_coreclk_configure(int sercom, int gclkgen, bool wrlock) uint16_t regval; uint8_t gclkcore; - /* Set up the SERCOMn_GCLK_ID_CORE clock */ + /* Set up the SERCOMN_GCLK_ID_CORE clock */ gclkcore = (uint8_t)SERCOM_GCLK_ID_CORE(sercom); regval = ((uint16_t)gclkcore << GCLK_CLKCTRL_ID_SHIFT); - /* Select and disable the SERCOMn_GCLK_ID_CORE generic clock */ + /* Select and disable the SERCOMN_GCLK_ID_CORE generic clock */ putreg16(regval, SAM_GCLK_CLKCTRL); @@ -94,7 +94,7 @@ void sercom_coreclk_configure(int sercom, int gclkgen, bool wrlock) while ((getreg16(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) != 0); - /* Select the SERCOMn_GCLK_ID_CORE source clock generator */ + /* Select the SERCOMN_GCLK_ID_CORE source clock generator */ regval |= (uint16_t)gclkgen << GCLK_CLKCTRL_GEN_SHIFT; @@ -102,7 +102,7 @@ void sercom_coreclk_configure(int sercom, int gclkgen, bool wrlock) putreg16(regval, SAM_GCLK_CLKCTRL); - /* Enable the SERCOMn_GCLK_ID_CORE generic clock, optionally locking + /* Enable the SERCOMN_GCLK_ID_CORE generic clock, optionally locking * further writes to this GCLK. */ @@ -149,7 +149,7 @@ void sercom_slowclk_configure(int sercom, int gclkgen) #endif #endif - /* Setup the SERCOMn_GCLK channel. SERCOM0-4 use a common channel, but + /* Setup the SERCOMN_GCLK channel. SERCOM0-4 use a common channel, but * SERCOM5 uses a different channel. Configuration should be done only * once. */ diff --git a/arch/arm/src/samd5e5/hardware/sam_gclk.h b/arch/arm/src/samd5e5/hardware/sam_gclk.h index 76fe78d600..c64e508a23 100644 --- a/arch/arm/src/samd5e5/hardware/sam_gclk.h +++ b/arch/arm/src/samd5e5/hardware/sam_gclk.h @@ -135,7 +135,7 @@ #define GCLK_CHAN_SDHCn_SLOW 3 /* SDHC0-1 Slow */ #define GCLK_CHAN_SDHC0_SLOW 3 /* SDHC0 Slow */ #define GCLK_CHAN_SDHC1_SLOW 3 /* SDHC1 Slow */ -#define GCLK_CHAN_SERCOMn_SLOW 3 /* SERCOM Slow (common) */ +#define GCLK_CHAN_SERCOMN_SLOW 3 /* SERCOM Slow (common) */ #define GCLK_CHAN_SERCOM0_SLOW 3 /* SERCOM0 Slow */ #define GCLK_CHAN_SERCOM1_SLOW 3 /* SERCOM1 Slow */ #define GCLK_CHAN_SERCOM2_SLOW 3 /* SERCOM2 Slow */ diff --git a/arch/arm/src/samd5e5/sam_sercom.c b/arch/arm/src/samd5e5/sam_sercom.c index 893be1121e..a7996c0d4b 100644 --- a/arch/arm/src/samd5e5/sam_sercom.c +++ b/arch/arm/src/samd5e5/sam_sercom.c @@ -155,7 +155,7 @@ void sercom_coreclk_configure(int sercom, int coregen, bool wrlock) DEBUGASSERT((unsigned)sercom < SAMD5E5_NSERCOM); - /* Set up the SERCOMn_GCLK_ID_CORE clock */ + /* Set up the SERCOMN_GCLK_ID_CORE clock */ corechan = g_corclk_channel[sercom]; sam_gclk_chan_enable(corechan, coregen, wrlock); @@ -179,7 +179,7 @@ void sercom_slowclk_configure(int sercom, int slowgen) { DEBUGASSERT((unsigned)sercom < SAMD5E5_NSERCOM); - /* Setup the SERCOMn_GCLK channel. */ + /* Setup the SERCOMN_GCLK channel. */ if (!g_slowclk_configured) { @@ -187,7 +187,7 @@ void sercom_slowclk_configure(int sercom, int slowgen) * of SERCOM modules and, hence, only need to configured once. */ - sam_gclk_chan_enable(GCLK_CHAN_SERCOMn_SLOW, slowgen, + sam_gclk_chan_enable(GCLK_CHAN_SERCOMN_SLOW, slowgen, BOARD_SERCOM_SLOWLOCK); /* The slow clock is now configured and should not be re=configured diff --git a/boards/arm/samd5e5/metro-m4/include/board.h b/boards/arm/samd5e5/metro-m4/include/board.h index d78ea69bee..fa9fb07b81 100644 --- a/boards/arm/samd5e5/metro-m4/include/board.h +++ b/boards/arm/samd5e5/metro-m4/include/board.h @@ -407,7 +407,7 @@ /* The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the * Main Clock Controller. The SERCOM uses two generic clocks: - * GCLK_SERCOMn_CORE and GCLK_SERCOM_SLOW. + * GCLK_SERCOMN_CORE and GCLK_SERCOM_SLOW. * The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while * working as a master. The slow clock (GCLK_SERCOM_SLOW) is only required * for certain functions and is common to all SERCOM modules. diff --git a/boards/arm/samd5e5/same54-xplained-pro/include/board.h b/boards/arm/samd5e5/same54-xplained-pro/include/board.h index fd5223c5f5..d9eebdccac 100644 --- a/boards/arm/samd5e5/same54-xplained-pro/include/board.h +++ b/boards/arm/samd5e5/same54-xplained-pro/include/board.h @@ -407,7 +407,7 @@ /* The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the * Main Clock Controller. * The SERCOM uses two generic clocks: - * GCLK_SERCOMn_CORE and GCLK_SERCOM_SLOW. + * GCLK_SERCOMN_CORE and GCLK_SERCOM_SLOW. * The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while * working as a master. The slow clock (GCLK_SERCOM_SLOW) is only required * for certain functions and is common to all SERCOM modules.