From 2d9e0f6a7674ddec03fcece2a7b72ac323b6b97b Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Tue, 8 Sep 2020 12:50:17 -0700 Subject: [PATCH] stm32f7:DMA Do not disqualify DMA capability based on cache alignment --- arch/arm/src/stm32f7/Kconfig | 11 +++++++++++ arch/arm/src/stm32f7/stm32_dma.c | 4 +++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index bb680d2e02..09c8f9e2bd 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -2634,6 +2634,17 @@ config STM32F7_DMACAPABLE Drivers then may use this information to determine if they should attempt the DMA or fall back to a different transfer method. +config STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED + bool "Do not disqualify DMA capability based on cache alignment" + depends on STM32F7_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH + default n + ---help--- + This option configures the stm32_dmacapable to not disqualify + DMA operations on memory that is not dcache aligned based solely + on the starting addresss and byte count. + Use this when ALL buffer extents are known to be aligned, but the + the count does not use the complete buffer. + menu "Timer Configuration" if SCHED_TICKLESS diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index 8040d17ce1..a1fbbcdd57 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -933,10 +933,12 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) if ((maddr & (ARMV7M_DCACHE_LINESIZE - 1)) != 0 || ((mend + 1) & (ARMV7M_DCACHE_LINESIZE - 1)) != 0) { - dmainfo("stm32_dmacapable:" + dmawarn("stm32_dmacapable:" " dcache unaligned maddr:0x%08x mend:0x%08x\n", maddr, mend); +#if !defined(CONFIG_STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; +#endif } # endif