arch/arm/src/samv7/sam_pwm.c: option to make channels synchronous
Make channels synchronous (i.e. share the same timebase) with the help of SAMV7_PWMx_CHy_SYNC defines. All the channels share the same timebase of channel 0, so this channel must be defined too. Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
This commit is contained in:
Pressl, Štěpán
Xiang Xiao
parent
b049b490b8
commit
297b3b0209
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@ -669,6 +669,18 @@ menuconfig SAMV7_PWM0
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if SAMV7_PWM0
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config SAMV7_PWM0_SYNC
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bool "PWM0 synchronous channels"
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depends on PWM_MULTICHAN
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default n
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---help---
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This option makes the synchronization between channels possible.
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This means every synchronized channel has the same clock, the
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same period and the same alignment. If any channel is defined
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as synchronous, channel 0 is defined as synchronous too because
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channel 0's counter is used by other synchronous channels.
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This option automatically defines channel 0 as synchronous.
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config SAMV7_PWM0_CH0
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bool "PWM0 Channel 0"
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default n
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@ -701,6 +713,11 @@ config SAMV7_PWM0_CH1_COMP
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depends on !SAMV7_PWM0_CH1_LONLY
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default n
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config SAMV7_PWM0_CH1_SYNC
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bool "Synchronous channel"
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depends on SAMV7_PWM0_SYNC
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default n
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endif
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config SAMV7_PWM0_CH2
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@ -718,6 +735,11 @@ config SAMV7_PWM0_CH2_COMP
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depends on !SAMV7_PWM0_CH2_LONLY
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default n
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config SAMV7_PWM0_CH2_SYNC
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bool "Synchronous channel"
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depends on SAMV7_PWM0_SYNC
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default n
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endif
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config SAMV7_PWM0_CH3
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@ -735,6 +757,11 @@ config SAMV7_PWM0_CH3_COMP
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depends on !SAMV7_PWM0_CH3_LONLY
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default n
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config SAMV7_PWM0_CH3_SYNC
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bool "Synchronous channel"
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depends on SAMV7_PWM0_SYNC
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default n
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endif
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menu "PWM Comparison units"
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@ -905,6 +932,18 @@ menuconfig SAMV7_PWM1
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if SAMV7_PWM1
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config SAMV7_PWM1_SYNC
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bool "PWM1 synchronous channels"
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depends on PWM_MULTICHAN
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default n
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---help---
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This option makes the synchronization between channels possible.
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This means every synchronized channel has the same clock, the
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same period and the same alignment. If any channel is defined
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as synchronous, channel 0 is defined as synchronous too because
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channel 0's counter is used by other synchronous channels.
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This option automatically defines channel 0 as synchronous.
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config SAMV7_PWM1_CH0
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bool "PWM1 Channel 0"
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default n
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@ -937,6 +976,11 @@ config SAMV7_PWM1_CH1_COMP
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depends on !SAMV7_PWM1_CH1_LONLY
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default n
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config SAMV7_PWM1_CH1_SYNC
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bool "Synchronous channel"
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depends on SAMV7_PWM1_SYNC
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default n
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endif
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config SAMV7_PWM1_CH2
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@ -954,6 +998,11 @@ config SAMV7_PWM1_CH2_COMP
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depends on !SAMV7_PWM1_CH2_LONLY
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default n
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config SAMV7_PWM1_CH2_SYNC
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bool "Synchronous channel"
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depends on SAMV7_PWM1_SYNC
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default n
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endif
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config SAMV7_PWM1_CH3
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@ -971,6 +1020,11 @@ config SAMV7_PWM1_CH3_COMP
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depends on !SAMV7_PWM1_CH3_LONLY
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default n
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config SAMV7_PWM1_CH3_SYNC
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bool "Synchronous channel"
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depends on SAMV7_PWM1_SYNC
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default n
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endif
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menu "PWM Comparison units"
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@ -65,6 +65,13 @@
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#define PWM_RES 65535
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#define COMP_UNITS_NUM 8
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/* Sync offset flags defines */
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#define CH0_SYNC_FLAG (1 << 0)
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#define CH1_SYNC_FLAG (1 << 1)
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#define CH2_SYNC_FLAG (1 << 2)
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#define CH3_SYNC_FLAG (1 << 3)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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@ -104,6 +111,7 @@ struct sam_pwm_s
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const struct sam_pwm_fault_s *fault;
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uint8_t channels_num; /* Number of channels */
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uintptr_t base; /* Base address of peripheral register */
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uint8_t sync; /* Flags of synchronized channels */
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};
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/* PWM driver methods */
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@ -229,6 +237,38 @@ static struct sam_pwm_fault_s g_pwm0_fault =
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.gpio_2 = GPIO_PWMC0_FI2,
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};
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/* Define sync flags */
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#ifdef CONFIG_SAMV7_PWM0_SYNC
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#define PWM0_CH0_SYNC_FLAG CH0_SYNC_FLAG
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#ifdef CONFIG_SAMV7_PWM0_CH1_SYNC
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#define PWM0_CH1_SYNC_FLAG CH1_SYNC_FLAG
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#else
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#define PWM0_CH1_SYNC_FLAG 0
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#endif
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#ifdef CONFIG_SAMV7_PWM0_CH2_SYNC
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#define PWM0_CH2_SYNC_FLAG CH2_SYNC_FLAG
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#else
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#define PWM0_CH2_SYNC_FLAG 0
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#endif
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#ifdef CONFIG_SAMV7_PWM0_CH3_SYNC
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#define PWM0_CH3_SYNC_FLAG CH3_SYNC_FLAG
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#else
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#define PWM0_CH3_SYNC_FLAG 0
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#endif
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#else
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#define PWM0_CH0_SYNC_FLAG 0
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#define PWM0_CH1_SYNC_FLAG 0
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#define PWM0_CH2_SYNC_FLAG 0
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#define PWM0_CH3_SYNC_FLAG 0
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#endif
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#define PWM0_SYNC_FLAGS (PWM0_CH0_SYNC_FLAG | PWM0_CH1_SYNC_FLAG | \
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PWM0_CH2_SYNC_FLAG | PWM0_CH3_SYNC_FLAG)
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static struct sam_pwm_s g_pwm0 =
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{
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.ops = &g_pwmops,
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@ -237,6 +277,7 @@ static struct sam_pwm_s g_pwm0 =
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.fault = &g_pwm0_fault,
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.channels_num = PWM0_NCHANNELS,
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.base = SAM_PWM0_BASE,
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.sync = PWM0_SYNC_FLAGS,
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};
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#endif /* CONFIG_SAMV7_PWM0 */
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@ -340,6 +381,38 @@ static struct sam_pwm_fault_s g_pwm1_fault =
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.gpio_2 = GPIO_PWMC1_FI2,
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};
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/* Define sync flags */
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#ifdef CONFIG_SAMV7_PWM1_SYNC
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#define PWM1_CH0_SYNC_FLAG CH0_SYNC_FLAG
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#ifdef CONFIG_SAMV7_PWM1_CH1_SYNC
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#define PWM1_CH1_SYNC_FLAG CH1_SYNC_FLAG
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#else
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#define PWM1_CH1_SYNC_FLAG 0
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#endif
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#ifdef CONFIG_SAMV7_PWM1_CH2_SYNC
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#define PWM1_CH2_SYNC_FLAG CH2_SYNC_FLAG
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#else
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#define PWM1_CH2_SYNC_FLAG 0
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#endif
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#ifdef CONFIG_SAMV7_PWM1_CH3_SYNC
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#define PWM1_CH3_SYNC_FLAG CH3_SYNC_FLAG
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#else
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#define PWM1_CH3_SYNC_FLAG 0
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#endif
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#else
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#define PWM1_CH0_SYNC_FLAG 0
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#define PWM1_CH1_SYNC_FLAG 0
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#define PWM1_CH2_SYNC_FLAG 0
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#define PWM1_CH3_SYNC_FLAG 0
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#endif
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#define PWM1_SYNC_FLAGS (PWM1_CH0_SYNC_FLAG | PWM1_CH1_SYNC_FLAG | \
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PWM1_CH2_SYNC_FLAG | PWM1_CH3_SYNC_FLAG)
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static struct sam_pwm_s g_pwm1 =
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{
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.ops = &g_pwmops,
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@ -348,6 +421,7 @@ static struct sam_pwm_s g_pwm1 =
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.fault = &g_pwm1_fault,
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.channels_num = PWM1_NCHANNELS,
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.base = SAM_PWM1_BASE,
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.sync = PWM1_SYNC_FLAGS,
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};
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#endif
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@ -496,10 +570,14 @@ static void pwm_set_output(struct pwm_lowerhalf_s *dev, uint8_t channel,
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width);
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}
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/* Enable the channel */
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regval = CHID_SEL(1 << channel);
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pwm_putreg(priv, SAMV7_PWM_ENA, regval);
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/* The enabling of a channel should be only done on unsynced channels */
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if (!(priv->sync & regval))
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{
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pwm_putreg(priv, SAMV7_PWM_ENA, regval);
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}
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}
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/****************************************************************************
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@ -684,6 +762,13 @@ static void pwm_set_polarity(struct pwm_lowerhalf_s *dev, uint8_t channel,
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struct sam_pwm_s *priv = (struct sam_pwm_s *)dev;
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uint16_t regval;
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/* Can't change polarity, if the channel is enabled! */
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if (pwm_getreg(priv, SAMV7_PWM_SR) & CHID_SEL(1 << channel))
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{
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return;
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}
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regval = pwm_getreg(priv, SAMV7_PWM_CMRX + (channel * CHANNEL_OFFSET));
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regval &= ~CMR_CPOL;
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regval &= ~CMR_DPOLI;
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@ -810,6 +895,14 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev)
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pwm_putreg(priv, SAMV7_PWM_FPV1, 0);
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pwm_putreg(priv, SAMV7_PWM_FPV2, 0);
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/* Enable synchronous channels. The flags in priv->sync
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* correspond to the lowest bits in PWM_SCM.
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* UPDM[1:0] is set to zero (manual update of deadtime, duty).
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*/
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regval = (uint32_t)priv->sync;
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pwm_putreg(priv, SAMV7_PWM_SCM, regval);
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return OK;
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}
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@ -864,9 +957,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
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const struct pwm_info_s *info)
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{
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struct sam_pwm_s *priv = (struct sam_pwm_s *)dev;
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#ifdef CONFIG_PWM_OVERWRITE
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uint32_t regval;
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#endif
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#ifdef CONFIG_PWM_MULTICHAN
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for (int i = 0; i < PWM_NCHANNELS; i++)
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@ -920,6 +1011,25 @@ static int pwm_start(struct pwm_lowerhalf_s *dev,
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#endif
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}
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}
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/* Perform the update of synchronized PWM channels */
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if (priv->sync)
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{
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regval = SCUC_UPDULOCK;
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/* Enable the Channel 0 if synchronous channels are used.
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* Channel 0's counter is used by all synchronous channels and
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* enabling CH0 results in enabling all synchronous channels.
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*
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* Enable the CH0 here after all setting all channel parameters,
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* because setting polarity configurations requires disabled
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* channels.
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*/
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pwm_putreg(priv, SAMV7_PWM_ENA, CHID_SEL(1));
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pwm_putreg(priv, SAMV7_PWM_SCUC, regval);
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}
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#else
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/* Set the frequency and enable PWM output just for first channel */
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@ -969,6 +1079,12 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev)
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pwm_putreg(priv, SAMV7_PWM_DIS, regval);
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}
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/* Just to be sure, disable all sync channels too */
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regval = pwm_getreg(priv, SAMV7_PWM_SCM);
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regval &= ~(CHID_SEL(1 << 0) | CHID_SEL(1 << 1) |
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CHID_SEL(1 << 2) | CHID_SEL(1 << 3));
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pwm_putreg(priv, SAMV7_PWM_SCM, regval);
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#else
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regval = CHID_SEL(1 << priv->channels[0].channel);
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pwm_putreg(priv, SAMV7_PWM_DIS, regval);
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