arm64: gicv3, add power up sequence for gc600/gc700
Summary: GICR_PWRR is a IMPLEMENTATION-DEFINED register for gc700/gc600, which is following gic v3 and v4. Please check GICR_PWRR define at TRM of GIC600/GIC700 for more detail Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
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@ -195,6 +195,7 @@
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#define GICR_TYPER 0x0008
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#define GICR_TYPER 0x0008
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#define GICR_STATUSR 0x0010
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#define GICR_STATUSR 0x0010
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#define GICR_WAKER 0x0014
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#define GICR_WAKER 0x0014
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#define GICR_PWRR 0x0024
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#define GICR_SETLPIR 0x0040
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#define GICR_SETLPIR 0x0040
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#define GICR_CLRLPIR 0x0048
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#define GICR_CLRLPIR 0x0048
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#define GICR_PROPBASER 0x0070
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#define GICR_PROPBASER 0x0070
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@ -299,6 +299,12 @@ static void gicv3_rdist_enable(unsigned long rdist)
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return;
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return;
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}
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}
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/* Power up sequence of the Redistributors for GIC600/GIC700
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* please check GICR_PWRR define at trm of GIC600/GIC700
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*/
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putreg32(0x2, rdist + GICR_PWRR);
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sys_clear_bit(rdist + GICR_WAKER, GICR_WAKER_PS);
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sys_clear_bit(rdist + GICR_WAKER, GICR_WAKER_PS);
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while (getreg32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA))
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while (getreg32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA))
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